T7630 datasheet(21/210 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

October 2000

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Lucent Technologies Inc.

Pin Information (continued)

Table 1. Pin Descriptions-Channel 1 and Channel 2 (continued)

* Iu indicates an internal pull-up.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

Symbol

Type*

Description

CH1 CH2

137

TND

Transmit Line Interface Negative-Rail Data. This signal is the transmit

framer negative NRZ output data. Data changes on the rising edge of TLCK.

In the single-rail mode, TND = 0.

136

TLCK

Transmit Framer Line Interface Clock. Optional 1.544 MHz DS1 or

2.048 MHz output signal from the transmit framer. TND and TPD data

changes on the rising edge of TLCK.

135

RLCK

Receive Framer Line Interface Clock. Valid when the FRAMER pin is

strapped to 0 V. This is the 1.544 MHz DS1 or 2.048 MHz input clock signal

used by the receive framer to latch RPD and RND data.

134

RFRMCK

Receive Framer Clock. Output receive framer clock signal used to clock out

the receive framer output signals. In normal operation, this is the recovered

receive line clock signal.

133

CKSEL

LIU System Clock Mode. This pin selects either a 16x rate clock for SYSCK

(CKSEL = 1) or a primary line rate clock for SYSCK (CKSEL = 0).

132

RFRMDATA

Receive Framer Data. This signal is the decoded data input to the receive

elastic store. During loss of frame alignment, this signal is forced to 1.

131

RFS

Receive Frame Sync. This active-high signal is the 8 kHz frame synchroni-

zation pulse generated by the receive framer.

130

RSSFS

Receive Framer Signaling Superframe Sync. This active-high signal is the

CEPT signaling superframe (multiframe) synchronization pulse in the receive

framer.

129

RCRCMFS

Receive Framer CRC-4 Multiframe Sync. This active-high signal is the

CEPT CRC-4 multiframe synchronization pulse in the receive framer.

128

RFDLCK

Receive Facility Data Link Clock. In DS1-DDS with data link access, this is

an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal. The receive

data link bit changes on the falling edge of RFDLCK.

127

RFDL

Receive Facility Data Link. Serial output facility data link bit stream

extracted from the receive line data stream by the receive framer. In DS1-

DDS with data link access, this is an 8 kbits/s signal; otherwise,

4 kbits/s. In the CEPT frame format, RFDL can be programmed to one of the

Sa bits of the NOT FAS frame TS0. During loss of frame alignment, this sig-

nal is 1.

126

TCHICK

TransmitrCHI Clock.

2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.

This clock must be free of jitter.

125

TCHIFS

I/O

Transmit CHI Frame Sync. Transmit CHI 8 kHz input frame synchronization

pulse phase-locked to TCHICK. In the CHI master mode, the transmit CHI

generates the 8 kHz frame sync to control the CHI.

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