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T7630 Datasheet(PDF) 2 Page - Agere Systems |
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T7630 Datasheet(HTML) 2 Page - Agere Systems |
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2 / 210 page ![]() Table of Contents Contents Page Preliminary Data Sheet T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) October 2000 2 Lucent Technologies Inc. Features ................................................................................................................................................................... 1 T1/E1 Line Interface Features............................................................................................................................... 1 Power Requirements and Package....................................................................................................................... 1 T1/E1 Framer Features ......................................................................................................................................... 1 Facility Data Link Features.................................................................................................................................... 1 Microprocessor Interface....................................................................................................................................... 1 Applications ........................................................................................................................................................... 1 Feature Descriptions .............................................................................................................................................. 12 T1/E1 Line Interface Features............................................................................................................................. 12 T1/E1 Framer Features ....................................................................................................................................... 12 Facility Data Link Features.................................................................................................................................. 13 User-Programmable Microprocessor Interface ................................................................................................... 13 Functional Description ............................................................................................................................................ 14 Pin Information ....................................................................................................................................................... 18 Line Interface Unit: Block Diagram ......................................................................................................................... 25 Line Interface Unit: Receive ................................................................................................................................... 25 Data Recovery..................................................................................................................................................... 25 Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator .............................................................. 26 Receive Line Interface Configuration Modes ...................................................................................................... 26 Line Interface Unit: Transmit .................................................................................................................................. 32 Output Pulse Generation..................................................................................................................................... 32 LIU Transmitter Configuration Modes ................................................................................................................. 33 LIU Transmitter Alarms ....................................................................................................................................... 33 DSX-1 Transmitter Pulse Template and Specifications ...................................................................................... 34 CEPT Transmitter Pulse Template and Specifications ....................................................................................... 36 Line Interface Unit: Jitter Attenuator ....................................................................................................................... 37 Generated (Intrinsic) Jitter................................................................................................................................... 37 Jitter Transfer Function ....................................................................................................................................... 37 Jitter Accommodation.......................................................................................................................................... 38 Jitter Attenuator Enable (Transmit or Receive Path)........................................................................................... 38 Line Interface Unit: Loopbacks ............................................................................................................................... 41 Full Local Loopback (FLLOOP)........................................................................................................................... 41 Remote Loopback (RLOOP) ............................................................................................................................... 41 Digital Local Loopback (DLLOOP) ...................................................................................................................... 41 Line Interface Unit: Other Features ........................................................................................................................ 41 LIU Powerdown (PWRDN) .................................................................................................................................. 41 Loss of Framer Receive Line Clock (LOFRMRLCK Pin)..................................................................................... 41 In-Circuit Testing and Driver High-Impedance State (3-STATE)......................................................................... 41 LIU Delay Values................................................................................................................................................. 42 SYSCK Reference Clock........................................................................................................................................ 42 Line Interface Unit: Line Interface Networks........................................................................................................... 43 LIU-Framer Interface .............................................................................................................................................. 46 LIU-Framer Physical Interface............................................................................................................................. 46 Interface Mode and Line Encoding...................................................................................................................... 47 DS1: Alternate Mark Inversion (AMI)................................................................................................................... 48 DS1: Zero Code Suppression (ZCS)................................................................................................................... 48 CEPT: High-Density Bipolar of Order 3 (HDB3).................................................................................................. 49 Frame Formats ....................................................................................................................................................... 49 T1 Framing Structures......................................................................................................................................... 49 |
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