T7630 datasheet(4/210 Pages) AGERE

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Contents

Page

Preliminary Data Sheet

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

October 2000

Lucent Technologies Inc.

Table of Contents (continued)

Test Access Port Controller............................................................................................................................... 121

Instruction Register ........................................................................................................................................... 123

Boundary-Scan Register ................................................................................................................................... 124

BYPASS Register.............................................................................................................................................. 124

IDCODE Register .............................................................................................................................................. 124

3-State Procedures ........................................................................................................................................... 124

Microprocessor Interface ...................................................................................................................................... 125

Overview ........................................................................................................................................................... 125

Microprocessor Configuration Modes................................................................................................................ 125

Microprocessor Interface Pinout Definitions...................................................................................................... 126

Microprocessor Clock (MPCLK) Specifications................................................................................................. 127

Microprocessor Interface Register Address Map .............................................................................................. 127

I/O Timing.......................................................................................................................................................... 127

Reset .................................................................................................................................................................... 134

Hardware Reset (Pin 43/139)............................................................................................................................ 134

Software Reset/Software Restart ...................................................................................................................... 134

Register Architecture ............................................................................................................................................ 135

Global Register Architecture................................................................................................................................. 139

Global Register Structure ..................................................................................................................................... 140

Primary Block Interrupt Status Register (GREG0) ............................................................................................ 140

Primary Block Interrupt Enable Register (GREG1) ........................................................................................... 140

Global Loopback Control Register (GREG2) .................................................................................................... 141

Global Loopback Control Register (GREG3) .................................................................................................... 141

Global Control Register (GREG4) ..................................................................................................................... 142

Device ID and Version Registers (GREG5—GREG7) ...................................................................................... 142

Line Interface Unit (LIU) Register Architecture..................................................................................................... 143

Line Interface Alarm Register ............................................................................................................................... 144

Alarm Status Register (LIU_REG0)................................................................................................................... 144

Line Interface Alarm Interrupt Enable Register .................................................................................................... 144

Alarm Interrupt Enable Register (LIU_REG1) ................................................................................................... 144

Line Interface Control Registers ........................................................................................................................... 145

LIU Control Register (LIU_REG2) ..................................................................................................................... 145

LIU Control Register (LIU_REG3) ..................................................................................................................... 145

LIU Control Register (LIU_REG4) ..................................................................................................................... 146

LIU Configuration Register (LIU_REG5) ........................................................................................................... 147

LIU Configuration Register (LIU_REG6) ........................................................................................................... 147

Framer Register Architecture ............................................................................................................................... 148

Framer Status/Counter Registers...................................................................................................................... 149

FDL Register Architecture .................................................................................................................................... 190

FDL Parameter/Control Registers (800—80E; E00—E0E) .................................................................................. 191

Register Maps ...................................................................................................................................................... 198

Global Registers................................................................................................................................................ 198

Line Interface Unit Parameter/Control and Status Registers ............................................................................ 198

Framer Parameter/Control Registers (Read-Write)........................................................................................... 199

Receive Framer Signaling Registers (Read-Only) ............................................................................................ 201

Framer Unit Parameter Register Map .............................................................................................................. 202

Transmit Signaling Registers (Read/Write) ....................................................................................................... 205

Facility Data Link Parameter/Control and Status Registers (Read-Write)........................................................ 206

Absolute Maximum Ratings................................................................................................................................. 207

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