TMUX03155 datasheet(88/120 Pages) AGERE

88 / 120 page

Agere Systems Inc.

Data Sheet

April 2001

TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer

Microprocessor Interface (continued)

Table 71. Register 103: Receive Low-Speed L-RDI Inhibit Control (R/W)

Table 72. Registers 104—106: Receive Low-Speed C1 Byte (R/W)

Table 73. Registers 107—109: Receive Low-Speed F1 Byte (R/W)

Table 74. Registers 110—115: Receive Low-Speed K1, K2 Byte Insert (R/W)

Address

Dec (Hex)

Bit

Name

Function

Reset

Default

103 (0x67)

RTILOC_LRDIINH

Receive Transmit Input Loss-of-Clock RDI-L

Inhibit. Control bits, when set to a logic 1, inhibit

the associated alarm from contributing to RDI-L

generation per STS-1/AU-3 frame.

103 (0x67)

5—3

RTLSLOF_LRDIINH[3—1]

Receive Transmit Low-Speed Loss-of-Frame

RDI-L Inhibit. Same as above.

111

103 (0x67)

2—0

RTLSOOF_LRDIINH[3—1]

Receive Transmit Low-Speed Out-of-Frame

RDI-L Inhibit. Same as above.

000

Address

Dec (Hex)

Bit

Name

Function

Reset

Default

104 (0x68)

105 (0x69)

106 (0x6A)

7—0

RC1DINS[1—3][7:0]

Receive C1 Data Insert. Register value is

inserted into the respective STS-1/AU-3 output

C1 byte.

0x00

Address

Dec (Hex)

Bit

Name

Function

Reset

Default

107 (0x6B)

108 (0x6C)

109 (0x6D)

7—0

RF1DINS[1—3][7:0]

Receive F1 Software Insert. Register value is

inserted into the respective STS-1/AU-3 output

F1 byte.

0x00

Address

Dec (Hex)

Bit

Name

Function

Reset

Default

110 (0x6E)

111 (0x6F)

7—3

7—0

RAPSINS1[12:8]

RAPSINS1[7:0]

Receive APS Insert. Register value is inserted

into the respective STS-1/AU-3 output K1 and

K2[7:3] bytes.

0x0000

112 (0x70)

113 (0x71)

7—3

7—0

RAPSINS2[12:8]

RAPSINS2[7:0]

114 (0x72)

115 (0x73)

7—3

7—0

RAPSINS3[12:8]

RAPSINS3[7:0]

110 (0x6E)

112 (0x70)

114 (0x72)

2—0

RK2DINS[3—1][2:0]

Receive K2 Data Insert. Register value is

inserted into the respective STS-1/AU-3 output

K2[2:0] bits.

000

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