TMUX03155 datasheet(68/120 Pages) AGERE

68 / 120 page

Agere Systems Inc.

Data Sheet

April 2001

TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer

Microprocessor Interface (continued)

Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W) (continued)

Table 37. Register 62: Transmit High-Speed Control Signals (R/W)

Address

Dec (Hex)

Bit

Name

Function

Reset

Default

61 (0x3D)

THSSCR

Transmit High-Speed Scramble Enable. Control

bit, when set to a logic 1, causes the output STS-3/

STM-1 (AU-4) signal to be scrambled; the signal is

not scrambled if set to a logic 0.

61 (0x3D)

RHS2THSLB

Receive High-Speed to Transmit High-Speed

Loopback Control. Control bit, when set to a logic

1, causes the receive STS-3/STM-1 (AU-4) input

signal to be looped back to the transmit high-speed

output; loopback is disabled when set to a logic 0.

61 (0x3D)

THSCHIZ

Transmit High-Speed Clock High-Impedance

(Control). Control signal, when set to a logic 1,

causes the output STS-3/STM-1 (AU-4) clock to be

placed in a high-impedance state; a logic 0 enables

the output driver.

61 (0x3D)

THSSHIZ

Transmit High-Speed Sync High-Impedance

(Control). Control signal, when set to a logic 1,

causes the output STS-3/STM-1 (AU-4) sync signal

to be placed in a high-impedance state; a logic 0

enables the output driver.

61 (0x3D)

THSDHIZ

Transmit High-Speed Data High-Impedance

(Control). Control signal, when set to a logic 1,

causes the output STS-3/STM-1 (AU-4) data sig-

nals to be placed in a high-impedance state; a logic

0 enables the output drivers.

Address

Dec (Hex)

Bit

Name

Function

Reset

Default

62 (0x3E)

7—6

TSS[1:0]

Transmit SS (Bits). These bits are used in the

STS-1 mode to set the SS bits when an unequipped

signal is being generated.

62 (0x3E)

TPFEBEINH

Transmit Path FEBE Inhibit. Control bit, when set

to a logic 1, disables hardware insertion of Path

FEBE (B3 errors) in the outgoing STM-1 (AU-4)

frame G1 byte; a logic 0 enables hardware insertion

of PFEBE. Only valid in AU-4 mode.

62 (0x3E)

TSFEBEINH

Transmit Section FEBE Inhibit. Control bit, when

set to a logic 1, disables hardware insertion of Sec-

tion FEBE (B2 errors) in the outgoing STS-3/STM-1

frame M1 byte; a logic 0 enables hardware insertion

of SFEBE.

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