TMUX03155 datasheet(30/120 Pages) AGERE

30 / 120 page

Agere Systems Inc.

Data Sheet

April 2001

TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer

Maintenance Functions (continued)

Common Maintenance and Control Functions (continued)

Bit or Block Count

The device allows all counters, except the pseudorandom error counter, to either count the actual number of bit

errors or the number of blocks (a block equals one frame) that contain an error (BITBLOCKCNT, 0x34).

The section and path FEBE counters count the actual number of bit errors or the number of blocks that contain an

error (FEBEBITBLOCKCNT, 0x34).

Transmit Functions

The transmit section addresses maintenance functions that are unique to the transmit direction.

Parity (B1, B2, B3)

The device will perform a bit interleaved BIP-8 parity (B1) calculation and will write these bits into the B1 section

overhead byte. The device will perform a bit interleaved BIP-24 parity (B2) calculation and will write these bits into

the B2 line overhead byte. The device will perform a bit interleaved BIP-8 parity (B3) calculation and will write these

bits into the B3 path overhead byte (AU-4 mode only).

The device can perform a B1 (THSB1ERRINS, 0x4C), B2 (THSB2ERRINS[3—1], 0x4C), and B3

(THSB3ERRINS, 0x4C) parity byte inversion via microprocessor control.

A1, A2 Error Enable

The device will allow, under software control, from 1 to 32 continuous frames to have errored A1A2 patterns in the

outgoing frame (TA1A2ERRINS[4:0], 0x4D and TA1A2ERREN, 0x04).

Section Trace/Growth Byte Insert (J0/Z0)

The device inserts the data written into TJ0DINS[7:0], 0x3F, TZ02DINS[7:0], 0x40, and TZ03DINS[7:0], 0x41 into

the outgoing J0/Z0 bytes.

Fault Location Insert (F1)

Via microprocessor control of TF1INS, 0x3E and TF1DINS[7:0], 0x42, data information may be inserted into the

outgoing F1 byte. Direct microprocessor insert has higher priority than the TOAC insert control bit

(TTOAC_F1[1:0], 0x51).

Sync Status Byte Insert (S1)

Via microprocessor control of TS1INS, 0x3E and TS1DINS[7:0]0x45, data information may be inserted into the

outgoing S1 byte. Direct microprocessor insert has higher priority than the TOAC insert control bit

(TTOAC_Z1[1:0], 0x51).

Automatic Protection Switch (APS) Insertion (K1[7:0], K2[7:3])

The device writes the K1 and K2 bytes into the transmit K1 and K2 overhead bytes (TAPSINS[12:0], 0x43,

0x44). The K1 and K2[7:3] bits will only change when both values are valid. The TAPSINS[4:0], 0x44 byte is the

trigger for updating the APS bytes in the outgoing frame.

TMUX03155 Datasheet(PDF) 30 Page - Agere Systems