AD9102 datasheet(4/36 Pages) AD

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AD9102

Data Sheet

Rev. 0 | Page 4 of 36

DC SPECIFICATIONS (1.8 V)

TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless

otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

RESOLUTION

Bits

ACCURACY @ 1.8 V

Differential Nonlinearity (DNL)

±1.5

LSB

Integral Nonlinearity (INL)

±1.4

LSB

DAC OUTPUTS

Offset Error

±0.00025

% of FSR

Gain Error Internal Reference—No Automatic IOUTFS Calibration

−1.0

+1.0

% of FSR

Full-Scale Output Current

VCC = 1.8 V

Output Resistance

200

MΩ

Output Compliance Voltage

−0.5

+1.0

DAC TEMPERATURE DRIFT

Gain

±228

ppm/°C

Reference Voltage

±131

ppm/°C

REFERENCE OUTPUT

Internal Reference Voltage with AVDD = 1.8 V

0.8

1.0

1.2

Output Resistance

kΩ

REFERENCE INPUT

Voltage Compliance

0.1

1.25

Input Resistance External Reference Mode

MΩ

DIGITAL TIMING SPECIFICATIONS (3.3 V)

TMIN to TMAX; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2; IOUTFS = 8 mA; maximum sample rate,

unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

DAC CLOCK INPUT (CLKIN)

Maximum Clock Rate

180

MSPS

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width High

6.25

Minimum Pulse Width Low

6.25

Setup Time SDIO to SCLK

4.0

Hold Time SDIO to SCLK

5.0

Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO

6.2

Setup Time CS to SCLK

4.0

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