AD9102 datasheet(21/36 Pages) AD

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Data Sheet

AD9102

Rev. 0 | Page 21 of 36

0.1µF

SCHOTTKY

DIODES:

HSM2812

CLK+

50Ω

CLKN

CLKP

Mini-Circuits®

ADT1-1WT, 1:1Z

XFMR

AD9102

Figure 39. Transformer Coupled Clock

DAC OUTPUT CLOCK EDGE

The DAC can be configured to output samples on the rising or

falling edge of the CLKP/CLKN clock input by configuring the

DAC_INV_CLK bit in the CLOCKCONFIG register (Register 0x02).

This functionality sets the DAC output timing resolution at

1/(2 × fCLKP/CLKN).

GENERATING SIGNAL PATTERNS

The AD9102 can generate three types of signal patterns under

control of its programmable pattern generator.



Continuous waveforms



Periodic pulse train waveforms that repeat indefinitely



Periodic pulse train waveforms that repeat a finite number

of times

RUN Bit

Setting the RUN bit in the PAT_STATUS register (Register 0x1E)

to 1 arms the AD9102 for pattern generation. Clearing this bit

shuts down the pattern generator as shown in Figure 43.

TRIGGER Pin

A falling edge on the TRIGGER pin starts the generation of a

pattern. If the RUN bit is set to 1, the falling edge of the TRIGGER

pin starts the pattern generation. As shown in Figure 41, the pattern

generator state goes to pattern on a number of CLKP/CLKN clock

cycles following the falling edge of the TRIGGER pin. This delay

is programmed in the PATTERN_DELAY bit field.

The rising edge on the TRIGGER pin is a request for termination

of pattern generation; see Figure 42.

PATTERN Bit (Read Only)

When the read only PATTERN bit in the PAT_STATUS register

is set to 1, it indicates that the pattern generator is in the pattern

on state. A 0 indicates that the pattern generator is in the

pattern off state.

Pattern Types



Continuous waveforms are output by the DAC for the

duration of the pattern on state of the pattern generator.

Continuous waveforms ignore pattern periods.



Periodic pulse trains that repeat indefinitely are waveforms

that are output once during each pattern period. Pattern

periods occur one after the other as long as the pattern

generator is in the pattern on state.



Periodic pulse trains that repeat a finite number of times

are the same as those that repeat indefinitely, except that

the waveforms are output during a finite number of

consecutive pattern periods.

PATTERN

EXECUTED

PATTERN

EXECUTED

PATTERN

EXECUTED

TRIGGER

DAC

PATTERN_PERIOD

START_DLY

DATA @

START_ADDR

DATA @

STOP_ADDR

Figure 40. Periodic Pulse Trains Output on All DACs

PATTERN GENERATOR PROGRAMMING

Figure 40 shows periodic pulse train waveforms as seen at the

output to each of the DACs. The waveform is generated in each

pattern period. The start delay (START_DLY) is the delay

between the start of each pattern period and the start of the

waveform. The DAC waveform is a digital signal stored in

SRAM and multiplied by the DAC digital gain factor. The

SRAM data is read using the DAC address counter.

Setting Pattern Period

Two register bit fields are used to set the pattern period. The

PAT_PERIOD_BASE field in the PAT_TIMEBASE register sets

the number of CLKP/CLKN clocks per PATTERN_PERIOD

LSB. The PATTERN_PERIOD is programmed in the

PAT_PERIOD register. The longest pattern period available is

65,535 × 16/fCLKP/N.

Setting Waveform Start Delay Base

The waveform start delay base is programmed in the

START_DELAY_BASE bits of the PAT_TIMEBASE register

(Register 0x28[3:0]). The START_DELAY register (Register 0x5C)

is described in the DAC Input Datapaths section. The start delay

base determines how many CLKP/CLKN clock cycles there are

per START_DELAY LSB.

tSU

tDLY = PATTERN_DELAY VALUE + 1

PATTERN

STARTS

TRIGGER

CLKP/

CLKN

PATTERN

GENERATOR

STATE

RUN BIT

PATTERN

GENERTAOR OFF

PATTERN

GENERTAOR ON

Figure 41. TRIGGER Pin Initiated Pattern Start with Pattern Delay

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