AD9102 datasheet(19/36 Pages) AD

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Data Sheet

AD9102

Rev. 0 | Page 19 of 36

DAC TRANSFER FUNCTION

The AD9102 DAC provides a differential current output,

IOUTP/IOUTN.

The DAC output current equations are as follows:

IOUTP = IOUTFS × DAC INPUT CODE/214

(1)

IOUTN = IOUTFS × ((214 − 1) − DAC INPUT CODE)/214 (2)

where DAC INPUT CODE = 0 to 214 − 1. Full-scale current or

DAC Gain IOUTFS is 32 times IREF.

IOUTFS = 32 × IREF

(3)

where IREF = VREFIO/RSET.

IREF is the current that flows through the IREF resistor. The IREF

resistor may be on or off chip at the users’ discretion. When an

on-chip RSET resistor is in use, DAC gain accuracy can be improved

by employing the built-in automatic gain calibration capability.

ANALOG CURRENT OUTPUTS

Optimum linearity and noise performance of DAC outputs can

be achieved when they are connected differentially to an amplifier

or a transformer. In these configurations, common-mode signals

at the DAC outputs are rejected.

The output compliance voltage specifications listed in Table 1 and

Table 2 must be adhered to for the performance specifications

in those tables to be met.

SETTING IOUTFS, DAC GAIN

As expressed in Equation 3, DAC gain (IOUTFS) is a function of

the reference voltage at the REFIO terminal and RSET.

Voltage Reference

The AD9102 contains an internal 1.0 V nominal band gap

reference. The internal reference can be used, or replaced by a

more accurate off-chip reference. An external reference can

provide tighter reference voltage tolerances and/or lower

temperature drift than the on-chip band gap.

By default, the on-chip reference is powered up and ready to be

used. When using the on-chip reference, the REFIO terminal

needs to be decoupled to AGND using a 0.1 μF capacitor as

shown in Figure 34.

CURRENT

SCALING

x32

AD9102

DAC

IOUTFS

RSET

0.1µF

REFIO

IREF

AVSS

FSADJ

VBG

1.0V

–

Figure 34. On-Chip Reference with External RSET Resistor

Table 13 summarizes reference connections and programming.

Table 13. Reference Operation

Reference Mode

REFIO Pin

Internal

Connect 0.1

F

capacitor

External

Connect off-chip reference

When using an external reference, it is recommended to apply

the external reference to the REFIO pin.

Programming Internal VREFIO

The internal REFIO voltage level is programmable.

When the internal voltage reference is in use, the BGDR field in

the lower six bits in Register 0x03 adjusts the VREFIO level. This

adds or subtracts up to 20% from the nominal band gap voltage

on REFIO. The voltage across the FSADJ resistor tracks this

change. As a result, IREF varies by the same amount. Figure 35

shows VREFIO vs. BGDR code for an on-chip reference with a

default voltage (BGDR = 0x00) of 1.04 V.

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

CODE

Figure 35. Typical VREFIO Voltage vs. BGDR

RSET Resistors

RSET in the where statement for Equation 3 can be an internal

resistor or a board level resistor of the user’s choosing

connected to the FSADJ terminal.

To make use of the on-chip RSET resistor, set Bit 15 of the FSADJ

program values for the on-chip RSET manually.

AUTOMATIC IOUTFS CALIBRATION

Many applications require tight DAC gain control. The AD9102

provides an automatic IOUTFS calibration procedure used with an

on-chip RSET resistor only. The voltage reference, VREFIO, can be

the on-chip reference or an off-chip reference. The automatic

calibration procedure does a fine adjustment of the internal RSET

value and the current, IREF.

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