AD9129BBC datasheet(46/68 Pages) AD

46 / 68 page

AD9119/AD9129

Data Sheet

Rev. 0 | Page 46 of 68

00.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.50

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0.5

1.0

NORMALIZED FREQUENCY (×π RAD/Sample)

Figure 140. FIR40 2× Interpolation Filter Plot, Pass-Band Ripple

Pipeline Delay (Latency)

The pipeline delay, or latency, of the AD9129 varies

, based on

the configuration that is chosen and can be calculated using the

following formula:

Pipeline_Total = Pipeline_Delay + 2×_Delay

+ Group_Delay + FIFO_Level

The values listed in Table 13 can be used, depending on the

mode of operation that is selected.

Table 13. Pipeline Delay Values for Each Block

Mode

Pipeline

Delay

(fDAC cycles)

Group

Delay

(fDAC cycles)

Total

Pipeline

(fDAC cycles)

Total

Delay

(fDAC cycles)

No 2× filter

N/A

With FIR25

117

119

With FIR40

141

150

The terms used in Table 13 are defined as follows:



Pipeline delay is the time from DAC code latched until the

DAC output begins to move.



Group delay is the time for the maximum amplitude pulse

to reach the DAC output, as compared to the first time the

output moves.



No 2× filter is the base pipeline delay, including data

interface, analog circuitry (six cycles), and data FIFO at

half-full/Position 3.



FIR25 is the 2× interpolator with 25 dB of out-of-band

rejection.



FIR40 is the 2× interpolator with 40 dB of out-of-band

rejection.

Note that the values for pipeline delay apply in both normal

mode and Mix-Mode. After the total delay through the digital

blocks is calculated, add the FIFO level to that delay to find the

total pipeline delay. Note that the pipeline delay can be considered

fixed, with the only ambiguity being the FIFO state. The FIFO

state can be initialized as part of the startup sequence to ensure

a four sample spacing and, therefore, a fixed pipeline delay, or

deterministic latency (see the Resetting the FIFO Data Level

section for more information).

To ensure repeatable pipeline delay over multiple power-up cycles,

the SYNC output of the DAC must be aligned with a known system

sync reference. Follow a calibration process that is similar to the

multiple DAC sync process (see the Multiple DAC Synchronization

section for more information) after each power-up event to align

the DAC to the system sync reference.

Power-Up Time

The AD9119/AD9129 have a power-down register (Register 0x01)

that enables the user to power down various portions of the DAC.

The power-up time for several usage cases is shown in Table 14.

The recommended way to power up the AD9119/AD9129 is

to power up all parts of the circuit with IREF disabled (by setting

Table 14. Power-Up Times for Several Usage Cases

State

Time (μs)

Power-Up

From 0x01 = 0xEF to 0x01 = 0x08

250

Clock Path Up

From 0x01 = 0x0C to 0x01 = 0x08

220

Wake-Up

From 0x01 = 0x48 to 0x01 = 0x08

INTERRUPT REQUESTS

The AD9119/AD9129 can provide the host processor with an

interrupt request output signal (IRQ), indicating that one or

more of the following events has occurred:



One of the clock controllers has established or lost lock.



A parity error has occurred.



A sample error detection status or result is ready.



The FIFO is nearing an overwrite status.

The IRQ output signal is an active low output signal that is available

on the IRQ pin (Pin H2). If used, connect the output to VDD via

a 10 kΩ pull-up resistor.

Each IRQ is enabled by setting the enable bits in Register 0x03

and Register 0x04 that have the same bit mapping as the IRQ

status bits in Registers 0x05 and Register 0x06. If an interrupt bit

is not enabled, a read request of that bit shows a direct readback

of the current state of the source. Thus, a read request of either

enabled to generate an interrupt. When an interrupt bit is enabled,

it captures a rising edge of the interrupt source and holds it,

even if the source subsequently returns to its zero state. It is

possible, for example, for the retimer lost interrupt enable and

retimer lock interrupt enable status bits (Register 0x03[1:0],

respectively) to be set when a controller temporarily loses lock

but then reestablishes lock before the IRQ is serviced by the host.

In such a case, the host should validate the present status of the

suspect block by reading back its current status bits. Based on

the status of these bits, the host can take appropriate action, if

required.

AD9129BBC Datasheet(PDF) 46 Page - Analog Devices

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