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A32100DX Datasheet(PDF) 15 Page - Actel Corporation |
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A32100DX Datasheet(HTML) 15 Page - Actel Corporation |
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15 / 98 page  15 Hi R e l F P GA s 3 200 DX T i m i n g Mo de l ( L ogi c Fu nct i o ns u s i n g Qu ad ra nt Cl oc ks ) * * Values shown for A32100DX–1 at worst-case military conditions. ** Load dependent. Output Delays Internal Delays Input Delays tINH = 0.0 ns tINSU = 0.7 ns I/O Module D Q tINGO = 4.0 ns tINPY = 1.9 ns t IRD1 = 2.2 ns Combinatorial Module tPD = 3.1 ns Sequential Logic Module I/O Module tRD1 = 1.3 ns tDLH = 6.3 ns I/O Module QUADRANT CLOCKS FMAX = 100 MHz Combin- atorial Logic included in tSUD D Q D Q tLH = 0.0 ns tLSU = 0.4 ns tGHL= 12.4 ns tDLH = 6.3 ns tENHZ = 11.5 ns tRD1 = 1.3 ns tCO = 3.1 ns tSU = 0.5 ns tHD = 0.0 ns Predicted Routing Delays G G Decode Module tPDD = 3.3 ns tRDD = 0.5 ns tRD2 = 1.9 ns tRD4 = 3.3 ns tCKH = 12 ns** |
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