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A32100DX Datasheet(PDF) 17 Page - Actel Corporation |
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A32100DX Datasheet(HTML) 17 Page - Actel Corporation |
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17 / 98 page  17 Hi R e l F P GA s 1 200 XL T i m i ng Mo de l * *Values shown for A1280XL–1 at worst-case military conditions. † Input module predicted routing delay. Output Delays Internal Delays Input Delays tINH = 0.0 ns tINSU = 0.4 ns I/O Module D Q tINGL = 3.7 ns tINYL = 1.7 ns t IRD2 = 5.2 ns† Combinatorial Logic Module tPD = 3.7 ns Sequential Logic Module I/O Module tRD1 = 1.7 ns tDLH = 6.6 ns I/O Module ARRAY CLOCKS FMAX = 110 MHz Combin- atorial Logic included in tSUD D Q D Q tOUTH = 0.0 ns tOUTSU = 0.4 ns tGLH = 5.9 ns tDLH = 6.6 ns tENHZ = 7.5 ns tRD1 = 1.7 ns tCO = 3.7 ns tSU = 0.4 ns tHD = 0.0 ns tRD4 = 3.7 ns tRD8 = 7.0 ns Predicted Routing Delays tCKH = 7.1 ns G G FO = 256 tRD2 = 2.5 ns tLCO = 10.7 ns (64 loads, pad-pad) |
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