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A32100DX Datasheet(PDF) 38 Page - Actel Corporation |
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A32100DX Datasheet(HTML) 38 Page - Actel Corporation |
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38 / 98 page  38 A1 42 5A T i m i n g C har a c t e r i st i c s (continued) (W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units CMOS Output Module Timing1 tDHS Data to Pad, High Slew 9.2 10.8 ns tDLS Data to Pad, Low Slew 17.3 20.3 ns tENZHS Enable to Pad, Z to H/L, High Slew 7.7 9.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 13.1 15.5 ns tENHSZ Enable to Pad, H/L to Z, High Slew 9.9 11.6 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 10.5 11.6 ns tCKHS IOCLK Pad to Pad H/L, High Slew 12.5 13.7 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 18.1 20.1 ns dTLHHS Delta Low to High, High Slew 0.06 0.07 ns/pF dTLHLS Delta Low to High, Low Slew 0.11 0.13 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.06 ns/pF Dedicated (Hard-Wired) I/O Clock Network tIOCKH Input Low to High (Pad to I/O Module Input) 3.0 3.5 ns tIOPWH Minimum Pulse Width High 3.9 4.4 ns tIOPWL Minimum Pulse Width Low 3.9 4.4 ns tIOSAPW Minimum Asynchronous Pulse Width 3.9 4.4 ns tIOCKSW Maximum Skew 0.5 0.5 ns tIOP Minimum Period 7.9 9.3 ns fIOMAX Maximum Frequency 125 100 MHz Dedicated (Hard-Wired) Array Clock Network tHCKH Input Low to High (Pad to S-Module Input) 4.6 5.3 ns tHCKL Input High to Low (Pad to S-Module Input) 4.6 5.3 ns tHPWH Minimum Pulse Width High 3.9 4.4 ns tHPWL Minimum Pulse Width Low 3.9 4.4 ns tHCKSW Maximum Skew 0.4 0.4 ns tHP Minimum Period 7.9 9.3 ns fHMAX Maximum Frequency 125 100 MHz Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes. |
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