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A32100DX Datasheet(PDF) 50 Page - Actel Corporation

Part # A32100DX
Description  HiRel FPGAs
PDF  98 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX Datasheet(HTML) 50 Page - Actel Corporation

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A3 21 00 DX Ti m i n g Ch ar ac te r i st i c s (continued)
(Wor s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad to Y
1.9
2.6
ns
tINGO
Input Latch Gate-to-Output
4.0
5.3
ns
tINH
Input Latch Hold
0.0
0.0
ns
tINSU
Input Latch Setup
0.7
0.9
ns
tILA
Latch Active Pulse Width
6.1
8.1
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.2
2.9
ns
tIRD2
FO=2 Routing Delay
2.8
3.8
ns
tIRD3
FO=3 Routing Delay
3.5
4.7
ns
tIRD4
FO=4 Routing Delay
3.5
4.7
ns
tIRD8
FO=8 Routing Delay
5.6
7.5
ns
Global Clock Network
tCKH
Input Low to High
FO=32
FO=635
6.5
7.9
8.7
10.6
ns
ns
tCKL
Input High to Low
FO=32
FO=635
6.6
8.8
8.8
11.8
ns
ns
tPWH
Minimum Pulse Width High
FO=32
FO=635
4.1
4.6
5.5
6.1
ns
ns
tPWL
Minimum Pulse Width Low
FO=32
FO=635
4.1
4.6
5.5
6.1
ns
ns
tCKSW
Maximum Skew
FO=32
FO=635
1.8
1.8
2.4
2.4
ns
ns
tSUEXT
Input Latch External Setup
FO=32
FO=635
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=635
3.0
3.8
4.0
5.1
ns
ns
tP
Minimum Period (1/fmax)
FO=32
FO=635
7.1
7.9
9.5
10.5
ns
ns
fHMAX
Maximum Datapath Frequency
FO=32
FO=635
140
126
105
95
MHz
MHz
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.



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