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AD7942

Rev. B | Page 16 of

Power Supply

The AD7942 is specified over a wide operating range from

2.3 V to 5.5 V. It has, unlike other low voltage converters, a

noise low enough to design a low supply (2.5 V) 14-bit resolu-

tion system with respectable performance. It uses two power

supply pins: a core supply, VDD, and a digital input/output

interface supply, VIO. VIO allows direct interface with any

logic between 1.8 V and VDD. To reduce the supplies needed,

the VIO and VDD can be tied together. The AD7942 is indepen-

dent of power supply sequencing between VIO and VDD.

Additionally, it is insensitive to power supply variations over

a wide frequency range, as shown in Figure 27.

FREQUENCY (kHz)

1000

100

10000

VDD = 5V

Figure 27. PSRR vs. Frequency

The AD7942 powers down automatically at the end of each

conversion phase and, therefore, the power scales linearly with

the sampling rate, as shown in Figure 28. This makes the part

ideal for low sampling rates (even rates of a few hertz) and low

battery-powered applications.

VDD = 5V

VDD = 2.5V

VIO

1000

0.1

0.001

100

1000

10000

100000

1000000

SAMPLING RATE (SPS)

Figure 28. Operating Current vs. Sampling Rate

Supplying the ADC from the Reference

For simplified applications, the AD7942, with its low operating

current, can be supplied directly using the reference circuit, as

shown in Figure 29. The reference line can be driven by either

•

The system power supply directly,

•

A reference voltage with enough current output capability,

such as the ADR43x, or

•

A reference buffer, such as the AD8031, that can also filter

the system power supply (see Figure 29).

AD8031

AD7942

VIO

REF

VDD

10µF

10Ω

10kΩ

(NOTE 1)

1µF

NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER.

1µF

Figure 29. Example of Application Circuit

DIGITAL INTERFACE

Although the AD7942 has a reduced number of pins, it offers

flexibility in its serial interface modes.

When in CS mode, the AD7942 is compatible with SPI, QSPI,

digital hosts, and DSPs (for example, Blackfin® ADSP-BF53x or

ADSP-219x). A 3-wire interface using the CNV, SCK, and SDO

signals minimizes wiring connections, which is useful, for

instance, in isolated applications. A 4-wire interface using the

SDI, CNV, SCK, and SDO signals allows CNV, which initiates

conversions, to be independent of the readback timing (SDI).

This is useful in low jitter sampling or simultaneous sampling

applications.

When in chain mode, the AD7942 provides a daisy-chain

feature using the SDI input for cascading multiple ADCs on

a single data line similar to a shift register.

The mode in which the part operates depends on the SDI level

when the CNV rising edge occurs. The CS mode is selected if

SDI is high and the chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, the chain mode is always selected.

In either mode, the AD7942 offers the flexibility to optionally

force a start bit in front of the data bits. This start bit can be

used as a busy signal indicator to interrupt the digital host and

trigger the data reading. Otherwise, without a busy indicator,

the user must time out the maximum conversion time prior

to readback.

The busy indicator feature is enabled as follows:

•

In the CS mode, if CNV or SDI is low when the ADC

conversion ends (see

and

Figure 33

Figure 37

•

In the chain mode, if SCK is high during the CNV rising

edge (see Figure 41).

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