AD7942

Rev. B | Page 17 of

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CS Mode 3-Wire Without Busy Indicator

This mode is most often used when a single AD7942 is

connected to an SPI-compatible digital host. The connection

diagram is shown in Figure 30 and the corresponding timing

diagram is shown in Figure 31.

With SDI tied to VIO, a rising edge on CNV initiates a conver-

sion, selects the CS mode, and forces SDO to high impedance.

When a conversion is initiated, it continues to completion irres-

pective of the state of CNV. For instance, it is useful to bring

CNV low to select other SPI devices, such as analog

multiplexers. However, CNV must be returned high before the

minimum conversion time and held high until the maximum

conversion time to avoid generating the busy signal indicator.

When the conversion is complete the AD7942 enters the acqui-

sition phase and powers down. When CNV goes low, the MSB

is output onto SDO. The remaining data bits are then clocked

by subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host also using the SCK falling edge allows a faster

reading rate provided it has an acceptable hold time. After the

14th SCK falling edge or when CNV goes high, whichever is

earlier, SDO returns to high impedance.

CNV

SCK

SDO

SDI

DATA IN

CLK

CONVERT

VIO

DIGITAL HOST

AD7942

Figure 30. CS Mode 3-Wire Without Busy Indicator

Connection Diagram (SDI High)

SDO

D13

D12

D11

D1

D0

SCK

12

3

12

13

14

CNV

CONVERSION

ACQUISITION

ACQUISITION

SDI = 1

Figure 31. CS Mode 3-Wire Without Busy Indicator, Serial Interface Timing (SDI High)