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DS90CF366 Datasheet(PDF) 8 Page - Texas Instruments |
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DS90CF366 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 20 page ![]() DS90CF366, DS90CF386 SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 www.ti.com Figure 14. DS90CF366 (Receiver) LVDS Input Strobe Position C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(1) + ISI (Inter-symbol interference)(2) Cable Skew—typically 10 ps–40 ps per foot, media dependent (1) Cycle-to-cycle jitter is less than 250 ps at 85 MHz. (2) ISI is dependent on interconnect length; may be zero. Figure 15. Receiver LVDS Input Skew Margin 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90CF366 DS90CF386 |
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