DS90CF366, DS90CF386

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SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

RECEIVER SUPPLY CURRENT

ICCRW

Receiver Supply Current Worst Case

f = 32.5 MHz

49

70

mA

Pattern,

f = 37.5 MHz

53

75

mA

DS90CF386 Figure 3,

f = 65 MHz

81

114

mA

Figure 6

f = 85 MHz

96

135

mA

ICCRW

Receiver Supply Current Worst Case

f = 32.5 MHz

49

60

mA

Pattern,

f = 37.5 MHz

53

65

mA

DS90CF366 Figure 3,

f = 65 MHz

78

100

mA

Figure 6

f = 85 MHz

90

115

mA

ICCRG

Receiver Supply Current, 16 Grayscale

f = 32.5 MHz

28

45

mA

Pattern, Figure 4, Figure 5,

f = 37.5 MHz

30

47

mA

Figure 6

f = 65 MHz

43

60

mA

f = 85 MHz

43

70

mA

ICCRZ

Power Down = Low Receiver Outputs Stay Low

140

400

μA

during Power Down Mode

(2)

Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

(1)

Symbol

Parameter

Min

Max

Units

CLHT

CMOS/TTL Low-to-High Transition Time Figure 6

2.0

3.5

ns

CHLT

CMOS/TTL High-to-Low Transition Time Figure 6

1.8

3.5

ns

RSPos0

Receiver Input Strobe Position for Bit 0 Figure 13,

f = 85 MHz

0.49

0.84

1.19

ns

Figure 14

RSPos1

Receiver Input Strobe Position for Bit 1

2.17

2.52

2.87

ns

RSPos2

Receiver Input Strobe Position for Bit 2

3.85

4.20

4.55

ns

RSPos3

Receiver Input Strobe Position for Bit 3

5.53

5.88

6.23

ns

RSPos4

Receiver Input Strobe Position for Bit 4

7.21

7.56

7.91

ns

RSPos5

Receiver Input Strobe Position for Bit 5

8.89

9.24

9.59

ns

RSPos6

Receiver Input Strobe Position for Bit 6

10.57

10.92

11.27

ns

RSKM

f = 85 MHz

290

ps

RCOP

RxCLK OUT Period Figure 7

11.76

T

50

ns

RCOH

RxCLK OUT High Time Figure 7

f = 85 MHz

4.5

5

7

ns

RCOL

RxCLK OUT Low Time Figure 7

4.0

5

6.5

ns

RSRC

RxOUT Setup to RxCLK OUT Figure 7

2.0

ns

RHRC

RxOUT Hold to RxCLK OUT Figure 7

3.5

ns

RCCD

5.5

7.0

9.5

ns

RPLLS

Receiver Phase Lock Loop Set Figure 9

10

ms

RPDD

Receiver Power Down Delay Figure 12

1

μs

(1)

(2)

Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter

pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows

for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).

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