DS90CF366, DS90CF386

SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013

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Pin Diagrams for TSSOP Packages

Figure 16. DS90CF386MTD

Figure 17. DS90CF366MTD

APPLICATIONS INFORMATION

POWER SEQUENCING AND POWERDOWN MODE

Outputs of the transmitter remain in TRI-STATE until the power supply reaches 2V. Clock and data outputs will

placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total power dissipation

for each device will decrease to 5

μW (typical).

The transmitter input clock may be applied prior to powering up and enabling the transmitter. The transmitter

input clock may also be applied after power up; however, the use of the PWR DOWN pin is required. Do not

power up and enable (PWR DOWN = HIGH) the transmitter without a valid clock signal applied to the TxCLK IN

pin.

The FPD Link chipset is designed to protect itself from accidental loss of power to either the transmitter or

receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs

(RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the

receiver inputs are controlled by a failsafe bias circuitry. The LVDS inputs are High-Z during initial power on and

power off conditions. Current is limited (5 mA per input) by the fixed current mode drivers, thus avoiding the

potential for latchup when powering the device.

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