M68HC08 datasheet(171/332 Pages) FREESCALE

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Universal Serial Bus Module (USB)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

Universal Serial Bus Module (USB)

171

The start of a packet (SOP) is signaled by the originating port by driving

the D+ and D– lines from the idle state (also referred to as the J state) to

the opposite logic level (also referred to as the K state). This switch in

levels represents the first bit of the sync field. Figure 11-6 shows the

data signaling and voltage levels for the start of packet and the sync

pattern.

Figure 11-6. SOP, Sync Signaling, and Voltage Levels

11.5.1.2 Packet Identifier Field

The packet identifier field is an 8-bit number comprised of the 4-bit

packet identification and its complement. The field follows the sync

pattern and determines the direction and type of transaction on the bus.

Table 11-2 shows the packet identifier values for the supported packet

types.

END OF SYNC

FIRST BIT OF PACKET

SOP

BUS IDLE

VOH (min.)

VSE (max)

VSE (min.)

VOL (min.)

VSS

Table 11-2. Supported Packet Identifiers

Packet Identifier Value

Packet Identifier Type

%1001

IN Token

%0001

OUT Token

%1101

SETUP Token

%0011

DATA0 Packet

%1011

DATA1 Packet

%0010

ACK Handshake

%1010

NAK Handshake

%1110

STALL Handshake

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