M68HC08 datasheet(181/332 Pages) FREESCALE

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Universal Serial Bus Module (USB)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

Universal Serial Bus Module (USB)

181

11.7.3 USB Control Logic

The USB control logic manages data movement between the CPU and

the transceiver. The control logic handles both transmit and receive

operations on the USB. It contains the logic used to manipulate the

transceiver and the endpoint registers.

The byte count buffer is loaded with the active transmit endpoints byte

count value during transmit operations. This same buffer is used for

receive transactions to count the number of bytes received and, upon

the end of the transaction, transfer that number to the receive endpoints

byte count register.

When transmitting, the control logic handles parallel-to-serial

conversion, CRC generation, NRZI encoding, and bit stuffing.

When receiving, the control logic handles sync detection, packet

identification, end-of-packet detection, bit (un)stuffing, NRZI decoding,

CRC validation, and serial-to-parallel conversion. Errors detected by the

control logic include bad CRC, timeout while waiting for EOP, and bit

stuffing violations.

11.8 I/O Registers

These I/O registers control and monitor USB operation:

•

USB address register (UADDR)

•

USB control registers 0–4 (UCR0–UCR4)

•

USB status registers 0–1 (USR0–USR1)

•

USB interrupt registers 0–2 (UIR0–UIR2)

•

USB endpoint 0 data registers 0–7 (UE0D0–UE0D7)

•

USB endpoint 1 data registers 0–7 (UE1D0–UE1D7)

•

USB endpoint 2 data registers 0–7 (UE2D0–UE2D7)

M68HC08 Datasheet(PDF) 181 Page - Freescale Semiconductor, Inc