M68HC08 datasheet(185/332 Pages) FREESCALE

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Universal Serial Bus Module (USB)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

Universal Serial Bus Module (USB)

185

11.8.3 USB Interrupt Register 1

EOPF — End-of-Packet Detect Flag

This read-only bit is set when a valid end-of-packet sequence is

detected on the D+ and D– lines. Software must clear this flag by

writing a logic 1 to the EOPFR bit.

Reset clears this bit. Writing to EOPF has no effect.

1 = End-of-packet sequence has been detected

0 = End-of-packet sequence has not been detected

RSTF — USB Reset Flag

This read-only bit is set when a valid reset signal state is detected on

the D+ and D– lines. If the URSTD bit of the configuration register

(CONFIG) is clear, this reset detection will generate an internal reset

signal to reset the CPU and other peripherals including the USB

module. If the URSTD bit is set, this reset detection will generate an

USB interrupt. This bit is cleared by writing a logic 1 to the RSTFR bit.

This bit also is cleared by a POR reset.

NOTE:

The USB bit in the SRSR (see 8.8.2 SIM Reset Status Register

(SRSR)) is also a USB reset indicator.

TXD2F — Endpoint 2 Data Transmit Flag

This read-only bit is set after the data stored in endpoint 2 transmit

buffers has been sent and an ACK handshake packet from the host is

received. Once the next set of data is ready in the transmit buffers,

software must clear this flag by writing a logic 1 to the TXD2FR bit.

Address:

$003A

Bit 7

654321

Bit 0

Read:

EOPF

RSTF

TXD2F

RXD2F

TXD1F

RESUMF

TXD0F

RXD0F

Write:

Reset:

00000000

= Unimplemented

Figure 11-17. USB Interrupt Register 1 (UIR1)

M68HC08 Datasheet(PDF) 185 Page - Freescale Semiconductor, Inc

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