IMX53IEC datasheet(121/173 Pages) FREESCALE

121 / 173 page

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

121

Figure 79. SPDIF Timing Diagram

Figure 80. STCLK Timing

4.7.16

SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial

synchronous interfaces are summarized in Table 81.

NOTE

•

The terms WL and BL used in the timing diagrams and tables refer to

Word Length (WL) and Bit Length (BL).

•

The SSI timing diagrams use generic signal names wherein the names

used in the i.MX53 Reference Manual are channel specific signal

names. For example, a channel clock referenced in the IOMUXC

chapter as AUD3_TXC appears in the timing diagram as TXC.

Table 81. AUDMUX Port Allocation

Port

Signal Nomenclature

Type and Access

AUDMUX port 1

SSI 1

Internal

AUDMUX port 2

SSI 2

Internal

AUDMUX port 3

AUD3

External— AUD3 I/O

AUDMUX port 4

AUD4

External— EIM or CSPI1 I/O through IOMUXC

AUDMUX port 5

AUD5

External— EIM or SD1 I/O through IOMUXC

AUDMUX port 6

AUD6

External— EIM or DISP2 through IOMUXC

AUDMUX port 7

SSI 3

Internal

SRCK

(Output)

srckp

srckph

srckpl

STCLK

(Input)

stclkp

stclkph

stclkpl

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