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IMX53IEC Datasheet(PDF) 119 Page - Freescale Semiconductor, Inc |
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IMX53IEC Datasheet(HTML) 119 Page - Freescale Semiconductor, Inc |
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119 / 173 page  Electrical Characteristics i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 119 Figure 77. Test Access Port Timing Diagram Figure 78. TRST Timing Diagram Table 79. JTAG Timing ID Parameter1,2 All Frequencies Unit Min Max SJ0 TCK frequency of operation 1/(3•TDC) 1 0.001 22 MHz SJ1 TCK cycle time in crystal mode 45 — ns SJ2 TCK clock pulse width measured at VM 2 22.5 — ns SJ3 TCK rise and fall times — 3 ns SJ4 Boundary scan input data set-up time 5 — ns SJ5 Boundary scan input data hold time 24 — ns SJ6 TCK low to output data valid — 40 ns SJ7 TCK low to output high impedance — 40 ns SJ8 TMS, TDI data set-up time 5 — ns TCK (Input) TDI (Input) TDO (Output) TDO (Output) TDO (Output) VIH VIL Input Data Valid Output Data Valid Output Data Valid TMS SJ8 SJ9 SJ10 SJ11 SJ10 TCK (Input) TRST (Input) SJ13 SJ12 |
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