EP3SE110 datasheet(337/341 Pages) ALTERA

337 / 341 page

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

1–327

Glossary

Altera Corporation

Stratix III Device Handbook, Volume 2

High-Speed I/O Block: Deserialization factor (width of parallel data bus).

JTAG Timing

Specifications

JTAG Timing Specifications are in the following figure:

——

PLL

Specifications

The block diagram shown in the following figure highlights the PLL Specification parameters:

Diagram of PLL Specifications (1)

Note:

(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.

——

Receiver differential input discrete resistor (external to Stratix III device).

Table 1.

Glossary Table (Part 2 of 4)

Letter

Subject

Definitions

TDO

TCK

tJPZX

tJPCO

tJPH

tJPXZ

tJCP

tJPSU

tJCL

tJCH

TDI

TMS

Core Clock

External Feedback

Reconfigurable in User Mode

Key

CLK

PFD

Switchover

VCO

CLKOUT Pins

GCLK

RCLK

fINPFD

fIN

fVCO

fOUT

fOUT_EXT

Counters

C0..C9

EP3SE110 Datasheet(PDF) 337 Page - Altera Corporation

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