EP3SE110 datasheet(338/341 Pages) ALTERA

338 / 341 page

1–328

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

Glossary

Stratix III Device Handbook, Volume 2

Altera Corporation

SW (sampling

window)

The period of time during which the data must be valid in order to capture it correctly. The

setup and hold times determine the ideal strobe position within the sampling window (the

following figure):

Timing Diagram

Single-ended

Voltage

Referenced I/O

Standard

The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input

signal values. The AC values indicate the voltage levels at which the receiver must meet its

timing specifications. The DC values indicate the voltage levels at which the final logic state of

the receiver is unambiguously defined. After the receiver input has crossed the AC value, the

receiver changes to the new logic state.

The new logic state is maintained as long as the input stays beyond the DC threshold. This

approach is intended to provide predictable receiver timing in the presence of input waveform

ringing (The following figure):

Single-Ended Voltage Referenced I/O Standard

High-Speed receiver/transmitter input and output clock period.

TCCS (channel-

to-channel-skew)

The timing difference between the fastest and slowest output edges, including tco variation

and clock skew, across channels driven by the same PLL. The clock is included in the TCCS

measurement (refer to the Timing Diagram figure under S in this table)

tDUTY

High-Speed I/O Block: Duty cycle on high-speed transmitter output clock.

Timing Unit Interval (TUI)

The timing budget allowed for skew, propagation delays, and data sampling window. (TUI =

1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)

tFA LL

Signal high-to-low transition time (80-20%)

tIN CC J

Cycle-to-cycle jitter tolerance on PLL clock input

tOUTPJ _I O

Period jitter on general purpose I/O driven by a PLL

tOU T PJ _D C

Period jitter on dedicated clock output driven by a PLL

tRISE

Signal low-to-high transition time (20-80%)

——

Table 1.

Glossary Table (Part 3 of 4)

Letter

Subject

Definitions

Bit Time

0.5 x TCCS

RSKM

Sampling Window

(SW)

RSKM

0.5 x TCCS

VIH(AC)

VIH(DC)

VREF

VIL(DC)

VIL(AC)

VOH

VOL

VCCIO

VSS

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