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AD9776A/AD9778A/AD9779A

Rev. B | Page 29 of 56

Table 14. 3-Wire Interface Register Description

Address

Bits

Parameter

Function

Default

Comm

0x00

SDIO bidirectional

0: use SDIO pin as input data only.

1: use SDIO as both input and output data.

0x00

LSB/MSB first

0: first bit of serial data is MSB of data byte.

1: first bit of serial data is LSB of data byte.

0x00

Software reset

Bit must be written with a 1 and then 0 to soft reset

the 3-wire interface register map.

0x00

Power-down mode

0: all circuitry is active.

1: disable all digital and analog circuitry, only

3-wire interface port is active.

0x00

Auto power-down enable

Controls auto power-down mode. See the Power-

Down and Sleep Modes section.

0x00

PLL lock indicator

(read only)

0: PLL is not locked.

1: PLL is locked.

Digital Control

0x01

7:6

Interpolation Factor[1:0]

00: 1× interpolation.

01: 2× interpolation.

10: 4× interpolation.

11: 8× interpolation.

0x01

5:2

Filter Modulation Mode[3:0]

See Table 19 for filter modes.

0000

0x01

DATACLK Delay[4]

Sets MSB of delay of REFCLK input to DATACLK

output.

0x01

Zero stuffing enable

0: zero stuffing off.

1: zero stuffing on.

0x02

Data format

0: twos compliment.

1: unsigned binary.

0x02

Single port

0: both P1D and P2D data ports enabled.

1: data for both DACs received on P1D data port.

0x02

Real mode

0: enable Q path for signal processing.

1: disable Q path data (internal Q channel clocks

disabled, I and Q modulators disabled).

0x02

DATACLK delay enable

Enables the DATACLK delay feature. More details

on this feature are shown in the Optimizing the

Data Input Timing section.

0x02

Inverse sinc enable

0: inverse sinc filter disabled.

1: inverse sinc filter enabled.

0x02

DATACLK invert

0: output DATACLK same phase as internal data

sampling clock, DCLK_SMP signal.

1: output DATACLK opposite phase as internal data

sampling clock, DCLK_SMP signal.

0x02

TxEnable invert

Inverts the polarity of Pin 39, the TXENABLE input

pin (also functions as IQSELECT).

0x02

Q first

0: in interleaved mode, the I data precedes the

Q data on the input port.

1: in interleaved mode, the Q data precedes the

I data on the input port.

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