AD9649

Rev. 0 | Page 7 of

32

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 4.

Parameter

Temp

AD9649-20/AD9649-40

AD9649-65

AD9649-80

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

80/160

260

320

MHz

Conversion Rate1

Full

3

20/40

3

65

3

80

MSPS

Full

50/25

15.38

12.5

ns

25.0/12.5

7.69

6.25

ns

Full

1.0

1.0

1.0

ns

Full

0.1

0.1

0.1

ps rms

DATA OUTPUT PARAMETERS

Full

3

3

3

ns

Full

3

3

3

ns

Full

0.1

0.1

0.1

ns

Pipeline Delay (Latency)

Full

8

8

8

Cycles

Wake-Up Time2

Full

350

350

350

μs

Standby

Full

600/400

300

260

ns

OUT-OF-RANGE RECOVERY TIME

Full

2

2

2

Cycles

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N

VIN

CLK+

CLK–

N – 8

N – 7

N – 6

N – 5

N – 4

DATA

DCO

Figure 2. CMOS Output Data Timing