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ADP2121

Rev. B | Page 17 of 20

APPLICATIONS INFORMATION

The external component selection for the ADP2121 applica-

tions circuit is driven by the load requirement and begins with

the selection of the inductor. After the inductor is chosen, CIN

and COUT can be selected. Components can be identified using

the selection guide and recommended selection tables in this

section.

INDUCTOR SELECTION

The high switching frequency of the ADP2121 allows for minimal

output voltage ripple, even with small inductors. Inductor sizing

is a trade-off between efficiency and transient response. A small

inductor leads to a larger inductor current ripple, which provides

better transient response but degrades efficiency. Due to the high

switching frequency of the ADP2121, multilayer ceramic inductors

can be used for an overall smaller solution size. Shielded ferrite

core inductors are recommended for their low core losses and

low electromagnetic interference (EMI).

As a guideline, the peak-to-peak current ripple of the inductor

is typically set to

ΔIL = 0.45 × ILOAD

(1)

where ILOAD is the maximum output current. The largest ripple

current, ΔIL, occurs at the maximum input voltage.

It is important that the inductor be capable of handling the

maximum peak inductor current, IPK, determined by the

following equation:

IPK = ILOAD(MAX) + ΔIL/2

(2)

The dc current rating of the inductor should be greater than the

calculated IPK to prevent core saturation. The ADP2121 is designed

for applications with a 0.47 µH inductor. Other values are not

recommended, and stable operation over all conditions is not

guaranteed with their use. Table 6 shows the available 0.47 µH

surface-mount inductors that have been tested with the ADP2121.

INPUT CAPACITOR SELECTION

The input capacitor must be able to support the maximum

input operating voltage and the maximum rms input current.

Select an input capacitor capable of withstanding the rms input

current for the maximum load current in the application using

the following equation:

OUT

MAX

OUT

rms

)

(

)

(

−

(3)

The input capacitor reduces the input voltage ripple caused by

the switch currents on the VIN pin. Place the input capacitor

as close as possible to the VIN pin.

In principle, different types of capacitors can be considered, but for

battery-powered applications, the best choice is the multilayer

ceramic capacitor, due to its small size and low equivalent series

resistance (ESR). Table 7 offers suggestions for suitable input

capacitors. All capacitors listed in the table are multilayer

ceramic capacitors.

It is recommended that the VIN pin be bypassed with a 2.2 µF

or larger ceramic input capacitor if the supply line has a distri-

buted capacitance of at least 10 μF. If not, then at least a 10 μF

capacitor is recommended on the input supply pin. The input

capacitor can be increased without any limit for better input

voltage filtering. X5R or X7R dielectrics with a voltage rating of

6.3 V or 10 V are recommended. Y5U and Z5U dielectrics are

not recommended, due to their poor temperature and dc bias

characteristics.

OUTPUT CAPACITOR SELECTION

The output capacitor selection affects both the output voltage ripple

and the loop dynamics of the converter. For a given loop crossover

frequency (the frequency at which the loop gain drops to 0 dB),

the maximum voltage transient excursion (overshoot) is inversely

proportional to the value of the output capacitor. The ADP2121

has been designed to operate with small ceramic capacitors in

the 4.7 µF to 10 µF range that have low ESR and equivalent

series inductance (ESL). These components are able, therefore,

to meet stringent output voltage ripple specifications. X5R or

X7R dielectrics with a voltage rating of 6.3 V are recommended.

Table 8 shows a list of output MLCC capacitors recommended

for ADP2121 applications. The minimum effective capacitance

required for stable operation is 1.5 µF.

When choosing output capacitors, it is also important to account

for the loss of capacitance due to output voltage dc bias. This

may result in using a capacitor with a higher rated voltage to

achieve the desired capacitance value. Additionally, if ceramic

output capacitors are used, the capacitor rms ripple current

rating should always meet the application requirements. The

rms ripple current is calculated as

)

(

)

(

)

(

)

(

MAX

OUT

MAX

OUT

rms

COUT

−

(4)

At nominal load currents, the converter operates in pulse

frequency mode (PFM), and the overall output voltage ripple is the

sum of the voltage spike caused by the output capacitor ESR plus

the voltage ripple caused by charging and discharging the

output capacitor.

ΔVOUT = ΔIL × (ESR + 1/(8 × COUT × fSW))

(5)

The largest voltage ripple occurs at the highest input voltage.

At light load currents, if MODE is set low, then the converter

operates in the power-saving mode (PFM), and the output

voltage ripple increases.

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