11242 datasheet(103/441 Pages) FREESCALE

103 / 441 page

4- 6

MC68340 USER’S MANUAL

MOTOROLA

There are eight arbitration levels for access to the intermodule bus (IMB). The SIM40 is

fixed at the highest level (above the programmable level 7), and the CPU32 is fixed at the

lowest level (below level 0). The direct memory access (DMA) module is the only other

module that can become bus master and arbitrate for the bus. It must be initialized with a

level other than 0 or 7.

The AVR contains bits that correspond to external interrupt levels that require an

autovector response. The SIM40 supports up to seven discrete external interrupt

requests. If the bit corresponding to an interrupt level is set in the AVR, the SIM40 returns

an autovector in response to the IACK cycle servicing that external interrupt request.

Otherwise, external circuitry must either return an interrupt vector or assert the external

AVEC signal.

4.2.2.2 INTERNAL BUS MONITOR. The internal bus monitor continually checks for the

bus cycle termination response time by checking the

DSACK

≈, BERR, and HALT status or

the

AVEC status during an IACK cycle. The monitor initiates a bus error if the response

time is excessive. The bus monitor feature cannot be disabled for internal accesses to an

internal module. The internal bus monitor cannot check the

DSACK

≈ response on the

external bus unless the MC68340 is the bus master. The BME bit in the system protection

control register (SYPCR) enables the internal bus monitor for internal-to-external bus

cycles. If the system contains external bus masters whose bus cycles must be monitored,

an external bus monitor must be implemented. In this case, the internal-to-external bus

monitor option must be disabled.

The bus cycle termination response time is measured in clock cycles, and the maximum-

allowable response time is programmable. The bus monitor response time period ranges

from 8 to 64 system clocks (see Table 4-8). These options are provided to allow for

different response times of peripherals that might be used in the system.

4.2.2.3 DOUBLE BUS FAULT MONITOR. A double bus fault is caused by a bus error or

address error during the exception processing sequence. The double bus fault monitor

responds to an assertion of

HALT on the internal bus. Refer to Section 3 Bus Operation

for more information. The DBF bit in the reset status register (RSR) indicates that the last

reset was caused by the double bus fault monitor. The double bus fault monitor reset can

be enabled by the DBFE bit in the SYPCR.

4.2.2.4 SPURIOUS INTERRUPT MONITOR. The spurious interrupt monitor issues

BERR

if no interrupt arbitration occurs during an IACK cycle. Normally, during an IACK cycle,

one or more internal modules recognize that the CPU32 is responding to interrupt

request(s) and arbitrate for the privilege of returning a vector or asserting

AVEC. (The

SIM40 reports and arbitrates for externally generated interrupts.) This feature cannot be

disabled.

4.2.2.5 SOFTWARE WATCHDOG. The SIM40 provides a software watchdog option to

prevent system lock-up in case the software becomes trapped in loops with no controlled

exit. Once enabled by the SWE bit in the SYPCR, the software watchdog requires a

special service sequence to be executed on a periodic basis. If this periodic servicing

action does not occur, the software watchdog times out and issues a reset or a level 7

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

11242 Datasheet(PDF) 103 Page - Freescale Semiconductor, Inc

11242 Datasheet(HTML) 103 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL