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EP3SE50 Datasheet(PDF) 78 Page - Altera Corporation

Part # EP3SE50
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE50 Datasheet(HTML) 78 Page - Altera Corporation

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1–68
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
Table 1–52 lists the EP3SL70 row pins input timing parameters for single-ended I/O
standards.
1.2-V HSTL
CLASS I
GCLK
t
su
-0.732
-0.731
-1.050 -1.145 -1.085
-1.037 -1.416 -1.145 -1.085 -1.037 -1.416
ns
t
h
0.856
0.856
1.222
1.338
1.303
1.245
1.616
1.338
1.303
1.245
1.616
ns
GCLK
PLL
t
su
-0.885
-0.885
-1.291 -1.406 -1.533
-1.471 -1.865 -1.406 -1.533 -1.471 -1.865
ns
t
h
1.138
1.138
1.659
1.818
1.989
1.905
2.306
1.818
1.989
1.905
2.306
ns
1.2-V HSTL
CLASS II
GCLK
t
su
-0.720
-0.719
-1.040 -1.134 -1.069
-1.021 -1.400 -1.134 -1.069 -1.021 -1.400
ns
t
h
0.844
0.844
1.212
1.327
1.287
1.229
1.600
1.327
1.287
1.229
1.600
ns
GCLK
PLL
t
su
-0.873
-0.873
-1.281 -1.395 -1.517
-1.455 -1.849 -1.395 -1.517 -1.455 -1.849
ns
t
h
1.126
1.126
1.649
1.807
1.973
1.889
2.290
1.807
1.973
1.889
2.290
ns
3.0-V PCI
GCLK
t
su
-0.720
-0.719
-1.040 -1.134 -1.069
-1.021 -1.400 -1.134 -1.069 -1.021 -1.400
ns
t
h
0.844
0.844
1.212
1.327
1.287
1.229
1.600
1.327
1.287
1.229
1.600
ns
GCLK
PLL
t
su
-0.873
-0.873
-1.281 -1.395 -1.517
-1.455 -1.849 -1.395 -1.517 -1.455 -1.849
ns
t
h
1.126
1.126
1.649
1.807
1.973
1.889
2.290
1.807
1.973
1.889
2.290
ns
3.0-V
PCI-X
GCLK
t
su
-0.823
-0.822
-1.153 -1.263 -1.311
-1.265 -1.644 -1.263 -1.311 -1.265 -1.644
ns
t
h
0.945
0.945
1.326
1.459
1.532
1.474
1.849
1.459
1.532
1.474
1.849
ns
GCLK
PLL
t
su
-0.976
-0.976
-1.394 -1.524 -1.762
-1.702 -2.093 -1.524 -1.762 -1.702 -2.093
ns
t
h
1.227
1.227
1.763
1.939
2.221
2.137
2.539
1.939
2.221
2.137
2.539
ns
Table 1–51. EP3SL70 Column Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
Table 1–52. EP3SL70 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-0.811
-0.836
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
ns
t
h
0.925
0.962
1.582
1.801
1.915
1.799
1.814
1.796
1.923
1.804
1.865
ns
GCLK
PLL
t
su
0.937
0.945
1.371
1.505
1.747
1.679
1.951
1.526
1.756
1.693
1.982
ns
t
h
-0.688
-0.684
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
ns
3.3-V
LVCMOS
GCLK
t
su
-0.811
-0.836
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
ns
t
h
0.925
0.962
1.582
1.801
1.915
1.799
1.814
1.796
1.923
1.804
1.865
ns
GCLK
PLL
t
su
0.937
0.945
1.371
1.505
1.747
1.679
1.951
1.526
1.756
1.693
1.982
ns
t
h
-0.688
-0.684
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768
ns
3.0-V LVTTL
GCLK
t
su
-0.817
-0.847
1.368
1.506
1.750
1.682
1.954
1.525
1.761
1.698
1.987
ns
t
h
0.931
0.973
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768
ns
GCLK
PLL
t
su
0.931
0.934
1.585
1.800
1.912
1.796
1.811
1.797
1.918
1.799
1.860
ns
t
h
-0.682
-0.673
1.368
1.506
1.750
1.682
1.954
1.525
1.761
1.698
1.987
ns



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