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EP3SE50 Datasheet(PDF) 87 Page - Altera Corporation |
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EP3SE50 Datasheet(HTML) 87 Page - Altera Corporation |
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87 / 341 page  Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–77 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1.2-V HSTL CLASS I 4mA GCLK tco 3.035 3.035 4.284 4.647 5.117 4.996 5.204 4.647 5.117 4.996 5.204 ns GCLK PLL t co 3.361 3.361 4.768 5.176 5.714 5.571 5.900 5.176 5.714 5.571 5.900 ns 6mA GCLK tco 3.026 3.026 4.275 4.638 5.108 4.987 5.195 4.638 5.108 4.987 5.195 ns GCLK PLL t co 3.353 3.353 4.759 5.167 5.705 5.562 5.888 5.167 5.705 5.562 5.888 ns 8mA GCLK t co 3.026 3.026 4.282 4.646 5.117 4.996 5.204 4.646 5.117 4.996 5.204 ns GCLK PLL t co 3.354 3.354 4.767 5.175 5.714 5.571 5.891 5.175 5.714 5.571 5.891 ns 10mA GCLK t co 3.016 3.016 4.269 4.632 5.103 4.982 5.190 4.632 5.103 4.982 5.190 ns GCLK PLL t co 3.343 3.343 4.754 5.162 5.700 5.557 5.885 5.162 5.700 5.557 5.885 ns 12mA GCLK t co 3.016 3.016 4.270 4.633 5.104 4.983 5.191 4.633 5.104 4.983 5.191 ns GCLK PLL t co 3.343 3.343 4.754 5.162 5.701 5.558 5.877 5.162 5.701 5.558 5.877 ns 1.2-V HSTL CLASS II 16mA GCLK t co 3.037 3.037 4.286 4.648 5.117 4.996 5.204 4.648 5.117 4.996 5.204 ns GCLK PLL tco 3.364 3.364 4.770 5.177 5.714 5.571 5.914 5.177 5.714 5.571 5.914 ns 3.0-V PCI — GCLK t co 3.140 3.140 4.331 4.684 5.142 5.021 5.229 4.684 5.142 5.021 5.229 ns GCLK PLL tco 3.467 3.467 4.815 5.211 5.739 5.596 5.945 5.211 5.739 5.596 5.945 ns 3.0-V PCI-X — GCLK t co 3.140 3.140 4.331 4.684 5.142 5.021 5.229 4.684 5.142 5.021 5.229 ns GCLK PLL t co 3.467 3.467 4.815 5.211 5.739 5.596 5.945 5.211 5.739 5.596 5.945 ns Table 1–53. EP3SL70 Column Pins Output Timing Parameters (Part 7 of 7) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V |
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