1

2

3

4

5

10

9

8

7

6

OVP

GND

TIMER

OUT

VIN

SENSE

GATE

EN

UVLO

nPGD

LM5060

SNVS628F – OCTOBER 2009 – REVISED APRIL 2013

www.ti.com

Connection Diagram

Figure 1. 10-Lead VSSOP

See Package Number DGS0010A

PIN DESCRIPTIONS

Pin

Name

Description

Applications Information

No.

A constant current sink (16

μA typical) at the SENSE pin flows through an external resistor to set

1

SENSE

Input Voltage Sense

the threshold for fault detection.

The operating voltage range is 5.5V to 65V. The internal power-on-reset (POR) circuit typically

2

VIN

Supply Voltage Input

switches to the active state when the VIN pin is greater than 5.1V. A small ceramic bypass

capacitor close to this pin is recommended to suppress noise.

An external resistor divider from the system input voltage sets the Over-Voltage turn-off

Over-Voltage

threshold. The GATE pin is pulled low when OVP exceeds the typical 2.0V threshold, but the

3

OVP

Protection Comparator

controller is not latched off. Normal operation resumes when the OVP pin falls below typically

Input

1.76V.

The UVLO pin is used as an input Under-Voltage Lock-Out by connecting this pin to a resistor

divider between input supply voltage and ground. The UVLO comparator is activated when EN is

Under-Voltage Lock-

4

UVLO

high. A voltage greater than typically 1.6V at the UVLO pin will release the pull down devices on

Out Comparator Input

the GATE pin and allow the output to gradually rise. A constant current sink (5.5 µA typical) is

provided to ensure the UVLO pin is low in an open circuit condition.

A voltage less than 0.8V on the EN pin switches the LM5060 to a low current shutdown state. A

voltage greater than 2.0V on the EN pin enables the internal bias circuitry and the UVLO

5

EN

Enable Input

comparator. The GATE pin pull-up bias is enabled when both EN and UVLO are in the high

state. A constant current sink (6 µA typical) is provided to ensure the EN pin is low in an open

circuit condition.

6

GND

Circuit ground

7

TIMER

Timing capacitor

pin exceeds the 2.0V threshold condition, the LM5060 will latch off the MOSFET and remain off

until either the EN, UVLO or VIN (POR) input is toggled low and then high.

8

nPGD

Fault Status

exceeds the SENSE pin voltage, the nPGD indicator is active (low = no fault).

9

OUT

Output VoltageSense

conditions.

Connect to the external MOSFET’s gate. A charge-pump driven constant current source (24 µA

typical) charges the GATE pin. An internal zener clamps the GATE pin at typically 16.8V above

10

GATE

Gate drive output

the OUT pin. The

ΔV/Δt of the output voltage can be reduced by connecting a capacitor from the

GATE pin to ground.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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