LM5060

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SNVS628F – OCTOBER 2009 – REVISED APRIL 2013

Since a single capacitor is used to set the delay time for multiple fault conditions, it is likely that some

compromise will need to be made between a desired delay time and a practical delay time.

MOSFET SELECTION

The external MOSFET (Q1) selection should be based on the following criteria:

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MOSFETs with low threshold voltages offer the advantage that during turn on they are more likely to remain

within their safe operating area (SOA) because the MOSFET reaches the ohmic region sooner for a given

gate capacitance.

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The safe operating area (SOA) of the MOSFET device and the thermal properties should be considered

relative to the maximum power dissipation possible during startup or shutdown.

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does not increase the junction temperature above the manufacturer’s recommendation.

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from gate to source to limit the applied gate voltage. The external zener diode forward current rating should

be at least 80 mA to conduct the full gate pull-down current during fault conditions.

INPUT and OUTPUT CAPACITORS

Input and output capacitors are not necessary in all applications. Any current that the external MOSFET conducts

in the on-state will decrease very quickly as the MOSFET turns off. All trace inductances in the design including

wires and printed circuit board traces will cause inductive voltage kicks during the fast termination of a

conducting current. On the input side of the LM5060 circuit this inductive kick can cause large positive voltage

spikes, while on the output side, negative voltage spikes are generated. To limit such voltage spikes, local

capacitance or clamp circuits can be used. The necessary capacitor value depends on the steady state input

voltage level, the level of current running through the MOSFET, the inductance of circuit board traces as well as

the transition speed of the MOSFET.

Since the exact amount of trace inductance is hard to predict, careful evaluation of the circuit board is the best

method to optimize the input or output capacitance or clamp circuits.

UVLO, OVP

The UVLO and OVP thresholds are programmed to enable the external MOSFET (Q1) when the input supply

voltage is within the desired operating range. If the supply voltage is low enough that the voltage at the UVLO pin

is below the UVLO threshold, Q1 is switched off by a 2.2 mA (typical) current sink at the GATE pin, denying

power to the load. The UVLO threshold has approximately 180 mV of hysteresis.

If the supply voltage is high enough that the voltage at the OVP pin is above the OVP threshold, the GATE pin is

pulled low with a 80 mA current sink. Hysteresis is provided for each threshold. The OVP threshold has

approximately 240 mV of hysteresis.

Option A: The configuration shown in Figure 29 requires three resistors (R1, R2, and R3) to set the thresholds.

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