AD607ARSZ datasheet(14/24 Pages) AD

14 / 24 page

REV. C

–14–

AD607

PRODUCT OVERVIEW

The AD607 provides most of the active circuitry required to

realize a complete low power, single-conversion superhetero-

dyne receiver, or most of a double-conversion receiver, at input

frequencies up to 500 MHz, and an IF from 400 kHz to 12 MHz.

The internal I/Q demodulators and their associated phase-

locked loop, which can provide carrier recovery from the IF,

support a wide variety of modulation modes, including

n-PSK, n-QAM, and AM. A single positive supply voltage of 3 V

is required (2.92 V minimum, 5.5 V maximum) at a typical

supply current of 8.5 mA at midgain. In the following discus-

sion, VP will be used to denote the power supply voltage, which

will be assumed to be 3 V.

Figure 13 shows the main sections of the AD607. It consists of a

variable gain UHF mixer and linear four-stage IF strip, which

together provide a voltage controlled gain range of more than

90 dB; dual demodulators, each comprising a multiplier fol-

lowed by a two-pole, 2 MHz low-pass filter; and a phase-locked

loop providing the inphase and quadrature clocks. A biasing

system with CMOS compatible power-down completes the

AD607.

Mixer

The UHF mixer is an improved Gilbert cell design, and can

operate from low frequencies (it is internally dc-coupled) up to

an RF input of 500 MHz. The dynamic range at the input of the

mixer is determined at the upper end by the maximum input

signal level of

±56 mV between RFHI and RFLO up to which the

mixer remains linear, and at the lower end by the noise level. It is

customary to define the linearity of a mixer in terms of the 1 dB

gain-compression point and third order intercept, which for the

AD607 are –15 dBm and –8 dBm, respectively, in a 50

Ω system.

RFHI

RFLO

IFLO

BPF

LOIP

MXOP

MIDPOINT

BIAS

GENERATOR

VMID

IFHI

BIAS

GENERATOR

VPS1

VPS2

PRUP

COM1

COM2

VMID

PTAT

VOLTAGE

IFOP

BPF OR

LPF

DMIP

IOUT

FDIN

FLTR

QOUT

GAIN

AD607

GREF

VQFO

Figure 13. Functional Block Diagram

40.2127ms

40.2377ms

40.2627ms

TRIGGER ON EXTERNAL AT POS. EDGE AT 40.0mV

TIMEBASE

MEMORY 1

TIMEBASE

MEMORY 2

TIMEBASE

DELTA T

START

= 500 s/DIV

= 100.0mV/DIV

= 5.00 s/DIV

= 60.00mV/DIV

= 5.00 s/DIV

= 15.7990 s

= 40.2327ms

DELAY

OFFSET

DELAY

OFFSET

DELAY

STOP

= 40.2377ms

= 154.0mV

= 40.2377ms

= 209.0mV

= 40.2377ms

= 40.2485ms

TPC 18. Power-Up Response Time to PLL Stable

GAIN VOLTAGE – V

0.5

1.5

2.5

TPC 19. Power Supply Current vs. Gain Control Voltage,

GREF = 1.5 V

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