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DDC112Y/2K Datasheet(PDF) 4 Page - Texas Instruments

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Part # DDC112Y/2K
Description  Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
PDF  34 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DDC112Y/2K Datasheet(HTML) 4 Page - Texas Instruments

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DDC112
4
SBAS085B
www.ti.com
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
1
IN1
Input 1: analog input for Integrators 1A and 1B. The
integrator that is active is set by the CONV input.
2
AGND
Analog Ground
3
CAP1B
External Capacitor for Integrator 1B
4
CAP1B
External Capacitor for Integrator 1B
5
CAP1A
External Capacitor for Integrator 1A
6
CAP1A
External Capacitor for Integrator 1A
7AVDD
Analog Supply, +5V Nominal
8
TEST
Test Control Input. When HIGH, a test charge is applied
to the A or B integrators on the next CONV transition.
9
CONV
Controls which side of the integrator is connected to
input. In continuous mode; CONV HIGH
→ side A is
integrating, CONV LOW
→ side B is integrating. CONV
must be synchronized with CLK (see Figure 2).
10
CLK
System Clock Input, 10MHz Nominal
11
DCLK
Serial Data Clock Input. This input operates the serial I/
O shift register.
12
DXMIT
Serial Data Transmit Enable Input. When LOW, this
input enables the internal serial shift register.
13
DIN
Serial Digital Input. Used to cascade multiple DDC112s.
14
DVDD
Digital Supply, +5V Nominal
15
DGND
Digital Ground
16
DOUT
Serial Data Output, Hi-Z when DXMIT is HIGH
17
DVALID
Data Valid Output. A LOW value indicates valid data is
available in the serial I/O register.
18
RANGE0
Range Control Input 0 (least significant bit)
19
RANGE1
Range Control Input 1
20
RANGE2
Range Control Input 2 (most significant bit)
21
AGND
Analog Ground
22
VREF
External Reference Input, +4.096V Nominal
23
CAP2A
External Capacitor for Integrator 2A
24
CAP2A
External Capacitor for Integrator 2A
25
CAP2B
External Capacitor for Integrator 2B
26
CAP2B
External Capacitor for Integrator 2B
27
AGND
Analog Ground
28
IN2
Input 2: analog input for Integrators 2A and 2B. The
integrator that is active is set by the CONV input.
PIN CONFIGURATION
Top View
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IN2
AGND
CAP2B
CAP2B
CAP2A
CAP2A
V
REF
AGND
RANGE2 (MSB)
RANGE1
RANGE0 (LSB)
DVALID
DOUT
DGND
IN1
AGND
CAP1B
CAP1B
CAP1A
CAP1A
AV
DD
TEST
CONV
CLK
DCLK
DXMIT
DIN
DV
DD
DDC112U



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