Electronic Components Datasheet Search
  English  ▼

X  

DDC112Y/2K Datasheet(PDF) 16 Page - Texas Instruments

Click here to check the latest version.
Part # DDC112Y/2K
Description  Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DDC112Y/2K Datasheet(HTML) 16 Page - Texas Instruments

Back Button DDC112Y/2K Datasheet HTML 12Page - Texas Instruments DDC112Y/2K Datasheet HTML 13Page - Texas Instruments DDC112Y/2K Datasheet HTML 14Page - Texas Instruments DDC112Y/2K Datasheet HTML 15Page - Texas Instruments DDC112Y/2K Datasheet HTML 16Page - Texas Instruments DDC112Y/2K Datasheet HTML 17Page - Texas Instruments DDC112Y/2K Datasheet HTML 18Page - Texas Instruments DDC112Y/2K Datasheet HTML 19Page - Texas Instruments DDC112Y/2K Datasheet HTML 20Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 34 page
background image
DDC112
16
SBAS085B
www.ti.com
FIGURE 13. Non-Continuous Mode Timing.
Ncont Mode
Figure 13 illustrates operation in the ncont mode. The
integrations come in pairs (that is, sides A/B or sides B/A)
followed by a time during which no integrations occur.
During that time, the previous integrations are being mea-
sured, reset and auto-zeroed. Before the DDC112 can
advance to states 3 or 6, both sides A and B must be
finished with the m/r/az cycle which takes time t10. When the
m/r/az cycles are completed, time t11 is needed to prepare
the next side for integration. This time is required for the
ncont mode because the m/r/az cycle of the ncont mode is
slightly different from that of the cont mode. After the first
integration ends, DVALID goes LOW in time t8. This is the
same time as in the cont mode. The second data will be
ready in time t9 after the first data is ready. One result of the
naming convention used in this application bulletin is that
when the DDC112 is operating in the
ncont mode, it passes
through both
ncont mode states and cont mode states. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1,
2, 3, 4...where 3 and 4 are cont mode states.
Ncont mode
by definition means that for some portion of the time, neither
side A nor B is integrating. States that perform an integration
are labeled
cont mode states while those that do not are
called
ncont mode states. Since integrations are performed
in the ncont mode, just not continuously, some cont mode
states must be used in an ncont mode state pattern.
SYMBOL
DESCRIPTION
VALUE (CLK = 10MHz)
VALUE (CLK = 15MHz)
t8
1st ncont mode data ready.
421.2
±0.3µs
280.8
±0.2µs
t9
2nd ncont mode data ready.
454.8
µs
303.2
µs
t10
Ncont mode m/r/az cycle.
910.8
µs
607.2
µs
t11
Prepare side for integration.
≥ 24.0µs
≥ 24.0µs
23
1
34
4
1
2
Int B
Int A
Int B
Int A
m/r/az B
m/r/az A
m/r/az A
m/r/az B
CONV
State
mbsy
m/r/az
Status
Integration
Status
DVALID
t
10
t
9
t
11
t
8
Side A
Data
Side B
Data
Side A
Data
Side B
Data



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com