DDC112YSLASH2K datasheet(18/34 Pages) TI

18 / 34 page

DDC112

SBAS085B

www.ti.com

FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode.

FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal.

CONV1

CONV2

State

mbsy

CONV

DVALID

State

Integration

Status

mbsy

Int B

Int A

Int B

Side A

Data

Side B

Data

Side A

Data

Int A

Looking at the state diagram, one can see that the CONV

pattern needed to generate a given state progression is not

unique. Upon entering states 1 or 8, the DDC112 remains in

those states until mbsy goes LOW, independent of CONV.

As long as the m/r/az cycle is underway, the state machine

ignores CONV (see Figure 9). The top two signals are

different CONV patterns that produce the same state.

This feature can be a little confusing at first, but it does allow

flexibility in generating ncont mode CONV patterns. For

example, the DDC112 Evaluation Fixture operates in the

ncont mode by generating a square wave with pulse width

< t6. Figure 17 illustrates operation in the ncont mode using

a 50% duty cycle CONV signal with TINT = 1620 CLK

periods. Care must be exercised when using a square wave

to generate CONV. There are certain integration times that

must be avoided since they produce very short intervals for

state 2 (or state 7 if CONV is inverted). As seen in the state

diagram, the state progresses from 2 to 3 as soon as CONV

is HIGH. The state machine does not insure that the duration

of state 2 is long enough to properly prepare the next side

for integration (t11). This must be done by the user with

proper timing of CONV. For example, if CONV is a square

wave with TINT = 3042 CLK periods, state 2 will only be 18

CLK periods long, therefore, t11 will not be met.

DDC112Y/2K Datasheet(PDF) 18 Page - Texas Instruments

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