DDC112YSLASH2K datasheet(8/34 Pages) TI

8 / 34 page

DDC112

SBAS085B

www.ti.com

THEORY OF OPERATION

The basic operation of the DDC112 is illustrated in Figure 1.

The device contains two identical input channels where each

performs the function of current-to-voltage integration fol-

lowed by a multiplexed analog-to-digital (A/D) conversion.

Each input has two integrators so that the current-to-voltage

integration can be continuous in time. The output of the four

integrators are switched to one delta-sigma (

∆Σ) converter

via a four input multiplexer. With the DDC112 in the continu-

ous integration mode, the output of the integrators from one

side of both of the inputs will be digitized while the other two

integrators are in the integration mode as illustrated in the

timing diagram in Figure 2. This integration and A/D conver-

sion process is controlled by the system clock, CLK. With a

10MHz system clock, the integrator combined with the delta-

sigma converter accomplishes a single 20-bit conversion in

approximately 220

µs. The results from side A and side B of

each signal input are stored in a serial output shift register.

The DVALID output goes LOW when the shift register

contains valid data.

The digital interface of the DDC112 provides the digital

results via a synchronous serial interface consisting of a data

clock (DCLK), a transmit enable pin (DXMIT), a valid data pin

(DVALID), a serial data output pin (DOUT), and a serial data

input pin (DIN). The DDC112 contains only one A/D con-

verter, so the conversion process is interleaved between the

two inputs, as shown in Figure 2. The integration and

conversion process is fundamentally independent of the data

retrieval process. Consequently, the CLK frequency and

DCLK frequencies need not be the same. DIN is only used

when multiple converters are cascaded and should be tied to

DGND otherwise. Depending on TINT, CLK, and DCLK, it is

possible to daisy-chain over 100 converters. This greatly

simplifies the interconnection and routing of the digital out-

puts in cases where a large number of converters are

needed.

Dual

Switched

Integrator

Dual

Switched

Integrator

∆Σ

Modulator

Digital

Filter

Control

Digital

Input/Output

DVALID

DXMIT

DOUT

DIN

DCLK

RANGE2

RANGE1

RANGE0

TEST

CONV

CLK

CAP1A

CAP1B

CAP2A

CAP2B

IN2

IN1

REF

DGND

AGND

Input 1

Input 2

IN1, Integrator A

IN1, Integrator B

IN2, Integrator A

IN2, Integrator B

Conversion in Progress

DVALID

IN1B

IN2B

IN1A

Integrate

IN2A

IN1B

IN2B

IN1A

IN2A

FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode).

FIGURE 1. Block Diagram.

DDC112Y/2K Datasheet(PDF) 8 Page - Texas Instruments

DDC112Y/2K Datasheet(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL