DOC7707 datasheet(259/307 Pages) ETC1

259 / 307 page

259

7707F–AVR–11/10

AT90USB82/162

Memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program Memory

Page is stored by loading the Write Program Memory Page instruction with the address

lines 15..8. Before issuing this command, make sure the instruction Load Extended

Address Byte has been used to define the MSB of the address. The extended address

byte is stored until the command is re-issued, i.e., the command needs only to be

issued for the first page, since the memory size is not larger than 64KWord. If polling

(RDY/BSY) is not used, the user must wait at least t

WD_FLASH before issuing the next

page. (See Table 25-15.) Accessing the serial programming interface before the Flash

write operation completes can result in incorrect programming.

The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is

first automatically erased before new data is written. If polling is not used, the user must

wait at least t

WD_EEPROM before issuing the next byte. (See Table 25-15.) In a chip

erased device, no 0xFFs in the data file(s) need to be programmed.

Any memory location can be verified by using the Read instruction which returns the

content at the selected address at serial output PDO. When reading the Flash memory,

use the instruction Load Extended Address Byte to define the upper address byte,

which is not included in the Read Program Memory instruction. The extended address

byte is stored until the command is re-issued, i.e., the command needs only to be

issued for the first page, since the memory size is not larger than 64KWord.

At the end of the programming session, RESET can be set high to commence normal

operation.

Power-off sequence (if needed):

Set RESET to “1”.

Turn V

CC power off.

Figure 25-11. Serial Programming Waveforms

Table 25-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

tWD_FLASH

4.5 ms

WD_EEPROM

9.0 ms

WD_ERASE

9.0 ms

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

SERIAL DATA OUTPUT

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