| Electronic Components Datasheet Search |
|
ADSP-21060 Datasheet(PDF) 35 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADSP-21060 Datasheet(HTML) 35 Page - Analog Devices |
|
35 / 64 page ![]() ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. H | Page 35 of 64 | March 2013 Three-State Timing—Bus Master, Bus Slave These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transi- tion cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. Table 21. Three-State Timing—Bus Master, Bus Slave 5 V and 3.3 V Unit Parameter Min Max Timing Requirements tSTSCK SBTS Setup Before CLKIN 12 + DT/2 ns tHTSCK SBTS Hold Before CLKIN 6 + DT/2 ns Switching Characteristics tMIENA Address/Select Enable After CLKIN1 –1.5 – DT/8 ns tMIENS Strobes Enable After CLKIN2 –1.5 – DT/8 ns tMIENHG HBG Enable After CLKIN –1.5 – DT/8 ns tMITRA Address/Select Disable After CLKIN3 0 – DT/4 ns tMITRS Strobes Disable After CLKIN2 1.5 – DT/4 ns tMITRHG HBG Disable After CLKIN 2.0 – DT/4 ns tDATEN Data Enable After CLKIN4 9 + 5DT/16 ns tDATTR Data Disable After CLKIN4 0 – DT/8 7 – DT/8 ns tACKEN ACK Enable After CLKIN4 7.5 + DT/4 ns tACKTR ACK Disable After CLKIN4 –1 – DT/8 6 – DT/8 ns tADCEN ADRCLK Enable After CLKIN –2 – DT/8 ns tADCTR ADRCLK Disable After CLKIN 8 – DT/4 ns tMTRHBG Memory Interface Disable Before HBG Low5 0 + DT/8 ns tMENHBG Memory Interface Enable After HBG High5 19 + DT ns 1 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns min. 2 Strobes = RD, WR, PAGE, DMAG, BMS, SW. 3 For ADSP-21060LC, specification is 0.25 – DT/4 ns max. 4 In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 5 Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode). Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion) MEMORY INTERFACE HBG MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW,PAGE, DMAGx. BMS (IN EPROM BOOT MODE) tMENHBG tMTRHBG |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |