www.ams.com/AS5013

Revision 1.11

12 - 32

AS5013

Datasheet - Detailed Descr i p ti on

7.5.4 I²C Modes

The AS5013 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a

receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A

master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the

bus. The AS5013 operates as a slave on the I²C bus. Connections to the bus are made through the open-drain I/O lines SDA and the input SCL.

Clock stretching is not included.

Automatic Increment of Address Pointer.

The AS5013 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent

from the address being valid or not.

Invalid Addresses.

If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible.

The address pointer is increased after each byte.

Reading.

When reading from a wrong address, the AS5013 slave data returns all zero. The address pointer is increased after each byte. Sequential read

over the whole address range is possible including address overflow.

Writing.

A write to a wrong address is not acknowledged by the AS5013 slave, although the address pointer is increased. When the address pointer

points to a valid address again, a successful write access is acknowledged. Page write over the whole address range is possible including

address overflow.

The following bus protocol has been defined:



Data transfer may be initiated only when the bus is not busy.



During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH

are interpreted as start or stop signals.

Accordingly, the following bus conditions have been defined:

Rise time of SCLH signal

after repeated START

condition and after an

acknowledge bit

External pull-up

source of 3mA

-

-

10

80

20

160

ns

Rise Time of SDA and

SCL Signals

120

-

-

-

-

ns

Fall time of SDA and SCL

signals

120

-

-

-

-

ns

Setup Time for STOP

Condition

600

-

160

-

160

-

ns

Noise margin at LOW level For each connected

device (including

hysteresis)

0.1VDDp

-

0.1VDDp

-

0.1VDDp

-

V

Noise margin at HIGH

level

0.2VDDp

-

0.2VDDp

-

0.2VDDp

-

V

2. After this time the first clock is generated.

3. A device must internally provide a minimum hold time (300n for Fast-mode, 80ns / max 150ns for High-speed mode) for the SDA signal

the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL

Symbol

Parameter

Condition

Fast-mode

HS-mode

1

Unit

Min

Max

Min

Max

Min

Max