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DM163006 Datasheet(PDF) 210 Page - Microchip Technology |
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DM163006 Datasheet(HTML) 210 Page - Microchip Technology |
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210 / 320 page ![]() PIC18C601/801 DS39541A-page 210 Advance Information 2001 Microchip Technology Inc. 19.2 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscil- lator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO pins of the device has been stopped; for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watch- dog Timer Wake-up). The TO bit in the RCON register will be cleared upon a WDT time-out. By default, the Watchdog Timer is disabled by configu- ration to allow software control over Watchdog Timer operation. If the WDT is enabled by configuration, soft- ware execution may not disable this function. When the Watchdog Timer is disabled by configuration, the SWDTEN bit in the WDTCON register enables/ disables the operation of the WDT. The WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT postscaler may be assigned by using configuration bits WDPS<3:1> in CONFIG2H register. If the Watchdog Timer is disabled by configu- ration, values for the WDT postscaler may be assigned using the SWDPS bits in the WDTCON register. 19.2.1 CONTROL REGISTER Register 19-5 shows the WDTCON register. This is a readable and writable register. It contains control bits to control the Watchdog Timer from user software. If the Watchdog Timer is enabled by configuration, this regis- ter setting is ignored. REGISTER 19-5: WDTCON REGISTER Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. 2: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SWDPS2 SWDPS1 SWDPS0 SWDTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ’0’ bit 3-1 SWDPS2:SWDPS0: Software Watchdog Timer Postscale Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if it is not disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown |
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