DM163006 datasheet(212/320 Pages) MICROCHIP

212 / 320 page

PIC18C601/801

DS39541A-page 212

Advance Information

 2001 Microchip Technology Inc.

19.3

Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

Upon entering into Power-down mode, the following

actions are performed:

Watchdog Timer is cleared and kept running.

PD bit in RCON register is cleared.

TO bit in RCON register is set.

Oscillator driver is turned off.

I/O ports maintain the status they had before the

SLEEP

instruction was executed.

To achieve lowest current consumption, follow these

steps before switching to Power-down mode:

Place all I/O pins at either VDD or VSS and

ensure no external circuitry is drawing current

from I/O pin.

Power-down A/D and external clocks.

Pull all hi-impedance inputs to high or low,

externally.

Place T0CKI at VSS or VDD.

Current consumption by PORTB on-chip pull-

ups should be taken into account and disabled,

if necessary.

The MCLR pin must be at a logic high level (VIHMC).

19.3.1

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

External RESET input on MCLR pin.

Watchdog

Timer

Wake-up

(if

WDT

was

enabled).

Interrupt from INT pin, RB port change, or a

peripheral interrupt.

The following peripheral interrupts can wake the device

from SLEEP:

TMR1 interrupt.

Timer1 must be operating as

an asynchronous counter.

TMR3 interrupt.

Timer3 must be operating as

an asynchronous counter.

CCP Capture mode interrupt.

Special event trigger (Timer1 in Asynchronous

mode using an external clock).

MSSP (START/STOP) bit detect interrupt.

MSSP transmit or receive in Slave mode

(SPI/I2C).

10. USART RX or TX (Synchronous Slave mode).

11. A/D conversion (when A/D clock source is RC).

Other peripherals cannot generate interrupts, since

during SLEEP, no on-chip clocks are present.

External MCLR Reset will cause a device RESET. All

other events are considered a continuation of program

execution and will cause a "wake-up". The TO and PD

bits in the RCON register can be used to determine the

cause of the device RESET. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared, if a WDT time-out occurred (and caused

wake-up).

When the SLEEP instruction is being executed, the next

instruction (PC + 2) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOP after the SLEEP instruction.

19.3.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If an interrupt condition (interrupt flag bit and inter-

rupt enable bits are set) occurs before the execu-

tion of a SLEEP instruction, the SLEEP instruction

will complete as a NOP. Therefore, the WDT and

WDT postscaler will not be cleared, the TO bit will

not be set and PD bits will not be cleared.

• If the interrupt condition occurs during or after

the execution of a SLEEP instruction, the device

will immediately wake-up from sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

postscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

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