ADS1278IPAPR datasheet(25/51 Pages) TI1

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AINP

AINN

=14k

eff

W ´ (6.75MHz/f

ESDProtection

AVDD

AGND

AVDD

AINP

9pF

AINN

AGND

OFF

SAMPLE

MOD

=1/f

ESD

Protection

AVDD

VREFN

VREFP

AGND

VREFP

VREFN

eff

´ (6.75MHz/f

)

MOD

5.2kW

N=numberofactivechannels.

ADS1274

ADS1278

www.ti.com

SBAS367F

– JUNE 2007 – REVISED FEBRUARY 2011

The ADS1274/78 uses switched-capacitor circuitry to

measure the input voltage. Internal capacitors are

charged by the inputs and then discharged. Figure 67

shows a conceptual diagram of these circuits. Switch

S2 represents the net effect of the modulator circuitry

in discharging the sampling capacitor; the actual

implementation is different. The timing for switches S1

and S2 is shown in Figure 68. The sampling time

(tSAMPLE) is the inverse of modulator sampling

frequency (fMOD) and is a function of the mode, the

Figure 69. Effective Input Impedances

CLKDIV input, and CLK frequency, as shown in

Table 6.

VOLTAGE REFERENCE INPUTS

(VREFP, VREFN)

The voltage reference for the ADS1274/78 ADC is

the differential voltage between VREFP and VREFN:

VREF = (VREFP – VREFN). The voltage reference is

common to all channels. The reference inputs use a

structure similar to that of the analog inputs with the

equivalent circuitry on the reference inputs shown in

Figure 70. As with the analog inputs, the load

presented by the switched capacitor can be modeled

with an effective impedance, as shown in Figure 71.

However, the reference input impedance depends on

the number of active (enabled) channels in addition to

fMOD. As a result of the change of reference input

impedance

caused

enabling

and

disabling

channels, the regulation and setting time of the

Figure 67. Equivalent Analog Input Circuitry

external reference should be noted, so as not to

affect the readings.

Figure 68. S1 and S2 Switch Timing for Figure 67

Table 6. Modulator Frequency (fMOD) Mode

Selection

MODE SELECTION

CLKDIV

fMOD

High-Speed

fCLK/4

High-Resolution

fCLK/4

Figure 70. Equivalent Reference Input Circuitry

fCLK/8

Low-Power

fCLK/4

fCLK/40

Low-Speed

fCLK/8

The

average

load

presented

the

switched

capacitor input can be modeled with an effective

differential impedance, as shown in Figure 69. Note

that the effective impedance is a function of fMOD.

Figure 71. Effective Reference Impedance

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