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ADS1278IPAPR Datasheet(PDF) 28 Page - Texas Instruments

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Part # ADS1278IPAPR
Description  Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital Converters
PDF  51 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1278IPAPR Datasheet(HTML) 28 Page - Texas Instruments

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CLK
DRDY
SYNC
t
NDR
t
SYN
t
SCSU
t
CSHD
FSYNC
ValidData
DOUT
SYNC
t
NDR
t
SYN
CLK
t
CSHD
t
SCSU
ADS1274
ADS1278
SBAS367F
– JUNE 2007 – REVISED FEBRUARY 2011
www.ti.com
Figure 73. Synchronization Timing (SPI Protocol)
Table 11. SPI Protocol
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCSHD
CLK to SYNC hold time
10
ns
tSCSU
SYNC to CLK setup time
5
ns
tSYN
Synchronize pulse width
1
CLK periods
tNDR
Time for new data to be ready
129
Conversions (1/fDATA)
Figure 74. Synchronization Timing (Frame-Sync Protocol)
Table 12. Frame-Sync Protocol
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCSHD
CLK to SYNC hold time
10
ns
tSCSU
SYNC to CLK setup time
5
ns
tSYN
Synchronize pulse width
1
CLK periods
tNDR
Time for new data to be ready(1)
127
128
Conversions (1/fDATA)
(1)
If SYNC is asynchronous to the FSYNC clock, then tNDR varies from 127 to 128 conversions, starting from the rising edge of SYNC. If
SYNC is made synchronous to the FSYNC clock, then tNDR is stable.
28
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© 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS1274 ADS1278



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