ADS1278IPAPR datasheet(8/51 Pages) TI1

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CLK

CPW

CLK

CPW

SCLK

DIST

DOHD

SPW

Bit23(MSB)

Bit22

Bit21

SPW

DOPD

MSBPD

DIHD

· · ·

CONV

DRDY

SCLK

DOUT

DIN

ADS1274

ADS1278

SBAS367F

– JUNE 2007 – REVISED FEBRUARY 2011

www.ti.com

SPI FORMAT TIMING

SPI FORMAT TIMING SPECIFICATION

For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V, unless otherwise noted.

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

tCLK

CLK period (1/fCLK)

(1)

10,000

tCPW

CLK positive or negative pulse width

tCONV

Conversion period (1/fDATA)

(2)

256

2560

tCLK

tCD

(3)

Falling edge of CLK to falling edge of DRDY

tDS

(3)

Falling edge of DRDY to rising edge of first SCLK to retrieve data

tCLK

tMSBPD

DRDY falling edge to DOUT MSB valid (propagation delay)

tSD

(3)

Falling edge of SCLK to rising edge of DRDY

tSCLK

(4)

SCLK period

tCLK

tSPW

SCLK positive or negative pulse width

0.4

tCLK

tDOHD

(3) (5)

SCLK falling edge to new DOUT invalid (hold time)

tDOPD

(3)

SCLK falling edge to new DOUT valid (propagation delay)

ns(6)

tDIST

New DIN valid to falling edge of SCLK (setup time)

tDIHD

(5)

Old DIN valid to falling edge of SCLK (hold time)

(1)

fCLK = 27MHz maximum.

(2)

Depends on MODE[1:0] and CLKDIV selection. See Table 8 (fCLK/fDATA).

(3)

Load on DRDY and DOUT = 20pF.

(4)

For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc.

(5)

tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is

> 4ns.

(6)

DOUT1, TDM mode, IOVDD = 3.15V to 3.45V, and DVDD = 1.7V to 1.9V.

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