ADS1278IPAPR datasheet(29/51 Pages) TI1

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CLK

DRDY/FSYNC

(1)

DOUT

(DiscreteDataOutputMode)

· · ·

PWDN

NDR

PWDN

-UpData

ostPower

DOUT1

(TDMMode,DynamicPosition)

NormalPosition

DataShiftsPosition

NormalPosition

DataRemainsinPosition

DOUT1

(TDMMode,FixedPosition)

ADS1274

ADS1278

www.ti.com

SBAS367F

– JUNE 2007 – REVISED FEBRUARY 2011

POWER-DOWN (PWDN)

3. Detect for non-zero data in the powered-up

channel.

The

channels

the

ADS1274/78

can

independently powered down by use of the PWDN

After powering up one or more channels, the

inputs. To enter the power-down mode, hold the

channels are synchronized to each other. It is not

respective PWDN pin low for at least two CLK cycles.

necessary to use the SYNC pin to synchronize them.

To exit power-down, return the corresponding PWDN

When a channel is powered down in TDM data

pin high. Note that when all channels are powered

format, the data for that channel are either forced to

down, the ADS1274/78 enters a microwatt (

μW)

zero (fixed-position TDM data mode) or replaced by

power state where all internal biasing is disabled. In

shifting the data from the next channel into the

this state, the TEST[1:0] input pins must be driven; all

vacated data position (dynamic-position TDM data

other input pins can float. The ADS1274/78 outputs

mode).

remain driven.

In Discrete data format, the data are always forced to

As shown in Figure 75 and Table 13, a maximum of

zero.

When

powering-up

channel

130 conversion cycles must elapse for SPI interface,

dynamic-position TDM data format mode, the channel

and

129

conversion

cycles

must

elapse

for

data remain packed until the data are ready, at which

Frame-Sync,

before

reading

data

after

exiting

time the data frame is expanded to include the

power-down. Data from channels already running are

just-powered channel data. See the Data Format

not affected. The user software can perform the

section for details.

required delay time in any of the following ways:

1. Count the number of data conversions after

taking the PWDN pin high.

2. Delay 129/fDATA or 130/fDATA after taking the

PWDN pins high, then read data.

(1) In SPI protocol, the timing occurs on the falling edge of DRDY/FSYNC. Powering down all channels forces DRDY/FSYNC high.

Figure 75. Power-Down Timing

Table 13. Power-Down Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tPWDN

PWDN pulse width to enter Power-Down mode

CLK periods

tNDR

Time for new data ready (SPI)

129

130

Conversions (1/fDATA)

tNDR

Time for new data ready (Frame-Sync)(1)

128

129

Conversions (1/fDATA)

(1)

FSYNC clock running prior to the rising edge of PWDN. If PWDN is asynchronous to the FSYNC clock, tNDR-FS varies from 127 to 128

conversions. If PWDN is made synchronous to FSYNC, then tNDR-FS is stable.

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