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GR712RC Datasheet(PDF) 32 Page - Aeroflex Circuit Technology

Part # GR712RC
Description  Dual-Core LEON3-FT SPARC V8 Processor
PDF  48 Pages
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Manufacturer  AEROFLEX [Aeroflex Circuit Technology]
Direct Link  http://www.aeroflex.com
Logo AEROFLEX - Aeroflex Circuit Technology

GR712RC Datasheet(HTML) 32 Page - Aeroflex Circuit Technology

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AEROFLEX GAISLER
32
GR712RC-DS
Copyright Aeroflex Gaisler AB
February 2013, Issue 2.0
2.4.12 Obsolete
Proprietary function not supported.
2.4.13 MIL-STD-1553B BC/RT/BM
The timing waveforms and timing parameters are shown in figure 17 and are defined in table 24.
Table 24. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)
Name
Parameter
Reference edge
Min
Max
Unit
t1553BRM0
clock to data output delay
rising 1553CK edge
2 1)
21 1)
ns
t1553BRM1
data input to clock setup
rising 1553CK edge
-
-
ns 2)
t1553BRM2
data input from clock hold
rising 1553CK edge
-
-
ns 2)
t1553BRM3
clock frequency
1553CK
16, 20, 24
MHz 3)
Note 1:
Parameter not measured during production test.
Note 2:
The 1553RXA, 1553RXAN, 1553RXB and 1553RXBN inputs are re-synchronized internally.
Note 3:
The core frequency must be lower than the internal system frequency: t1553BRM3 < FCLK
Figure 17. Timing waveforms
t1553BRM0
1553TXA/TXAN
1553CK
1553RXA/RXAN
t1553BRM2
t1553BRM1
1553RXB/RXBN
1553TXB/TXBN
1553TXINHA, 1553TXINHB
1553RXENA, 1553RXENB



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