GR712RC datasheet(21/48 Pages) AEROFLEX

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AEROFLEX GAISLER

GR712RC-DS

February 2013, Issue 2.0

2.4

AC electrical performance characteristics

All measured AC parameters have been tested with a 50 pF - 70 pF capacitive load on the outputs.

Transition time measurements have been tested at a voltage level of 1.4 V. Equivalent load chart is

provided in the product speciﬁcation [PS.]

2.4.1

Clock

The timing waveforms and timing parameters are shown in ﬁgure 3 and are deﬁned in table 11.

Table 11. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)

Name

Parameter

Reference

Min

Max

Unit

TINCLK

input clock period without DLL

INCLK

FINCLK

input clock frequency without DLL 2)

INCLK

100

MHz

TINCLK_HIGH

input clock high phase without DLL 5)

INCLK

4.5

TINCLK_LOW

input clock low phase without DLL 5)

INCLK

4.5

TINCLK

input clock period with DLL 1)

INCLK

22 3)

FINCLK

input clock frequency with DLL 1) 2)

INCLK

46 3)

MHz

DCINCLK

input frequency duty cycle with DLL

INCLK

TINCLK_HIGH

input clock high phase with DLL 5)

INCLK

TINCLK_LOW

input clock low phase with DLL 5)

INCLK

TCLK

internal system clock period 4) 5) 6)

FCLK

internal system clock frequency 2) 4) 5) 6)

100

MHz

Note 1:

For the system clock, the DLL provides a times 2 multiplication of the input frequency.

Note 2:

TINCLK = 1/FINCLK, TCLK = 1/FCLK

Note 3:

Parameter not measured during production test.

Note 4:

Applies to the system clock only (i.e. processor and AMBA clock) only. SpaceWire clocks are dis-

cussed in section 2.4.9.

Note 5:

The maximum internal system clock frequency is speciﬁed by the parameters TCLK and FCLK.

The parameters TINCLK and FINCLK specify the what the clock input pin and the DLL can support,

and not what the internal logic can support.

Note 6:

The internal system clock frequency is limited by the timing of the memory interface towards external

synchronous memory components.

Figure 3. Timing waveforms

INCLK

TINCLK

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